TY - CHAP A1 - Wildgrube, Fabian A1 - Ehrett, Pete A1 - Trojahn, Paul A1 - Membarth, Richard A1 - Beckmann, Bradford A1 - Baumeister, Dominik A1 - Chajdas, Matthäus T1 - GPUs All Grown-Up: Fully Device-Driven SpMV Using GPU Work Graphs T2 - ISCA ´25: Proceedings of the 52nd Annual International Symposium on Computer Architecture N2 - Sparse matrix-vector multiplication (SpMV) is a key operation across high-performance computing, graph analytics, and many more applications. In these applications, the matrix characteristics, notably non-zero elements per row, can vary widely and impact which algorithm performs best. Thus, Graphics Processing Unit (GPU) SpMV algorithms often rely on costly preprocessing to determine what per-row algorithm to select to achieve high performance. In this work we combine SpMV preprocessing and the subsequent per-row processing on the GPU by leveraging the novel “Work Graphs” GPU programming model—initially designed for graphics applications—for dynamic on-device self-scheduling. Work Graphs allow for fine-grain dataflow execution of individual workgroups using emerging hardware and firmware support. As soon as preprocessing has generated sufficient work, workgroups of individual processing kernels are self-scheduled and executed, interleaved with those of other kernels. This improves cache locality and eliminates host interaction altogether. Across a suite of 59 sparse matrices, the best of various novel Work Graphs SpMV implementations outperforms state-of-the-art rocSPARSE “LRB” for a single SpMV by up to 7.19 × (mean: 3.35 ×, SD: 1.89). Furthermore, it achieves much more stable performance across various sparsity patterns than the rocSPARSE CSR-General algorithm, and even beats the advanced rocSPARSE CSR-Adaptive algorithm for up to 92 consecutive SpMV calculations. In addition, compared to rocSPARSE LRB, it reduces code complexity by 75%. Its memory footprint for supporting data structures is a fixed ∼ 25 MiB independent of matrix size, compared to rocSPARSE LRB’s data structures that scale with matrix size to hundreds of megabytes. Overall, this work showcases the performance potential of emerging dynamic on-device scheduling techniques for GPU compute applications. UR - https://doi.org/10.1145/3695053.3731060 Y1 - 2025 UR - https://doi.org/10.1145/3695053.3731060 UR - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:573-58868 SN - 979-8-4007-1261-6 SP - 1777 EP - 1791 PB - ACM CY - New York ER - TY - CHAP A1 - Devillers, Hugo A1 - Kurtenacker, Matthias A1 - Membarth, Richard A1 - Lemme, Stefan A1 - Kenzel, Michael A1 - Yazici, Ömercan A1 - Slusallek, Philipp ED - Knoll, Aaron ED - Peters, Christoph T1 - No More Shading Languages: Compiling C++ to Vulkan Shaders T2 - High-Performance Graphics - Symposium Papers N2 - Graphics APIs have traditionally relied on shading languages, however, these languages have a number of fundamental defects and limitations. By contrast, GPU compute platforms offer powerful, feature-rich languages suitable for heterogeneous compute. We propose reframing shading languages as embedded domain-specific languages, layered on top of a more general language like C++, doing away with traditional limitations on pointers, functions, and recursion, to the benefit of programmability. This represents a significant compilation challenge because the limitations of shaders are reflected in their lower-level representations. We present the Vcc compiler, which allows conventional C and C++ code to run as Vulkan shaders. Our compiler is complemented by a simple shading library and exposes GPU particulars as intrinsics and annotations. We evaluate the performance of our compiler using a selection of benchmarks, including a real-time path tracer, achieving competitive performance compared to their native CUDA counterparts. UR - https://doi.org/10.2312/hpg.20251167 Y1 - 2025 UR - https://doi.org/10.2312/hpg.20251167 UR - https://diglib.eg.org/handle/10.2312/hpg20251167 UR - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:573-60151 SN - 978-3-03868-291-2 PB - The Eurographics Association CY - Goslar ER - TY - CHAP A1 - Müller, André A1 - Schmidt, Bertil A1 - Membarth, Richard A1 - Leißa, Roland A1 - Hack, Sebastian T1 - AnySeq/GPU: A Novel Approach for Faster Sequence Alignment on GPUs T2 - Proceedings of the 36th ACM International Conference on Supercomputing (ICS-2022) UR - https://doi.org/10.1145/3524059.3532376 Y1 - 2022 UR - https://doi.org/10.1145/3524059.3532376 SN - 978-1-4503-9281-5 PB - ACM CY - New York ER - TY - JOUR A1 - Ravedutti Lucio Machado, Rafael A1 - Schmitt, Jonas A1 - Eibl, Sebastian A1 - Eitzinger, Jan A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Köstler, Harald T1 - tinyMD: Mapping molecular dynamics simulations to heterogeneous hardware using partial evaluation JF - Journal of Computational Science UR - https://doi.org/10.1016/j.jocs.2021.101425 KW - Molecular dynamics KW - Partial evaluation KW - High performance computing KW - Load balancing Y1 - 2021 UR - https://doi.org/10.1016/j.jocs.2021.101425 SN - 1877-7503 VL - 2021 IS - 54 PB - Elsevier CY - Amsterdam ER - TY - CHAP A1 - Amiri, Puya A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Leißa, Roland A1 - Hack, Sebastian T1 - FLOWER: a Comprehensive Dataflow Compiler for High-Level Synthesis T2 - Proceedings of the 2021 International Conference on Field-Programmable Technology (ICFPT) UR - https://doi.org/10.1109/ICFPT52863.2021.9609930 KW - high-level synthesis KW - dataflow KW - compiler KW - FPGA KW - transformations KW - high-performance computing Y1 - 2021 UR - https://doi.org/10.1109/ICFPT52863.2021.9609930 SN - 978-1-6654-2010-5 PB - IEEE CY - Piscataway (NJ) ER - TY - JOUR A1 - Özkan, M. Akif A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Teich, Jürgen A1 - Hannig, Frank T1 - AnyHLS: High-Level Synthesis with Partial Evaluation JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ITCSDI) UR - https://doi.org/10.1109/TCAD.2020.3012172 KW - Field programmable gate arrays KW - functional programming KW - high level synthesis KW - image processing Y1 - 2020 UR - https://doi.org/10.1109/TCAD.2020.3012172 SN - 1937-4151 VL - 39 IS - 11 SP - 3202 EP - 3214 PB - IEEE CY - New York ER - TY - CHAP A1 - Müller, André A1 - Schmidt, Bertil A1 - Hildebrandt, Andreas A1 - Membarth, Richard A1 - Leißa, Roland A1 - Kruse, Matthis A1 - Hack, Sebastian T1 - AnySeq: A High Performance Sequence Alignment Library based on Partial Evaluation T2 - Proceedings: 2020 IEEE 34th International Parallel and Distributed Processing Symposium (IPDPS 2020) UR - https://doi.org/10.1109/IPDPS47924.2020.00109 KW - Libraries KW - Computer architecture KW - Generators KW - Bioinformatics KW - Hardware KW - Field programmable gate arrays KW - Two dimensional displays Y1 - 2020 UR - https://doi.org/10.1109/IPDPS47924.2020.00109 SN - 978-1-7281-6876-0 SN - 1530-2075 SP - 1030 EP - 1040 PB - IEEE CY - Los Alamitos ER - TY - JOUR A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Slusallek, Philipp T1 - Rodent: Generating Renderers without Writing a Generator JF - ACM Transactions on Graphics (TOG) UR - https://doi.org/10.1145/3306346.3322955 KW - Rendering KW - Ray-tracing KW - Generator KW - Partial Evaluation Y1 - 2019 UR - https://doi.org/10.1145/3306346.3322955 SN - 1557-7368 SN - 0730-0301 VL - 38 IS - 4 PB - ACM CY - New York ER - TY - CHAP A1 - Membarth, Richard A1 - Dutta, Hritam A1 - Hannig, Frank A1 - Teich, Jürgen ED - Stenström, Per ED - Silvano, Cristina ED - Bertels, Koen ED - Schulte, Michael T1 - Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards T2 - Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC) UR - https://doi.org/10.1007/978-3-662-58834-5_1 KW - CUDA KW - OpenCL KW - Image processing KW - Mapping methodology KW - Streaming application Y1 - 2019 UR - https://doi.org/10.1007/978-3-662-58834-5_1 SN - 978-3-662-58834-5 SN - 978-3-662-58833-8 SP - 1 EP - 20 PB - Springer CY - Berlin ER - TY - JOUR A1 - Leißa, Roland A1 - Boesche, Klaas A1 - Hack, Sebastian A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Müller, André A1 - Schmidt, Bertil T1 - AnyDSL: a partial evaluation framework for programming high-performance libraries JF - Proceedings of the ACM on Programming Languages N2 - This paper advocates programming high-performance code using partial evaluation. We present a clean-slate programming system with a simple, annotation-based, online partial evaluator that operates on a CPS-style intermediate representation. Our system exposes code generation for accelerators (vectorization/parallelization for CPUs and GPUs) via compiler-known higher-order functions that can be subjected to partial evaluation. This way, generic implementations can be instantiated with target-specific code at compile time. In our experimental evaluation we present three extensive case studies from image processing, ray tracing, and genome sequence alignment. We demonstrate that using partial evaluation, we obtain high-performance implementations for CPUs and GPUs from one language and one code base in a generic way. The performance of our codes is mostly within 10%, often closer to the performance of multi man-year, industry-grade, manually-optimized expert codes that are considered to be among the top contenders in their fields. UR - https://doi.org/10.1145/3276489 KW - partial evaluation KW - high-performance KW - parallelization KW - vectorization KW - GPU computing KW - library design Y1 - 2018 UR - https://doi.org/10.1145/3276489 UR - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:573-28104 SN - 2475-1421 VL - 2 IS - OOPSLA PB - ACM CY - New York ER - TY - CHAP A1 - Özkan, M. Akif A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Teich, Jürgen A1 - Hannig, Frank T1 - A Journey into DSL Design using Generative Programming BT - FPGA Mapping of Image Border Handling through Refinement T2 - Fifth International Workshop on FPGAs for Software Programmers (FSP 2018) Y1 - 2018 UR - https://www.vde-verlag.de/proceedings-de/564723009.html SN - 978-3-8007-4723-8 SP - 64 EP - 72 PB - VDE Verlag CY - Berlin ER - TY - CHAP A1 - Schmitt, Jonas A1 - Köstler, Harald A1 - Eitzinger, Jan A1 - Membarth, Richard T1 - Unified Code Generation for the Parallel Computation of Pairwise Interactions Using Partial Evaluation T2 - Proceedings 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018 UR - https://doi.org/10.1109/ISPDC2018.2018.00012 KW - molecular dynamics KW - code generation KW - partial evaluation KW - gpu KW - neighbor lists Y1 - 2018 UR - https://doi.org/10.1109/ISPDC2018.2018.00012 SN - 978-1-5386-5330-2 SP - 17 EP - 24 PB - IEEE CY - Piscataway (NJ) ER - TY - CHAP A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Moll, Simon A1 - Leißa, Roland A1 - Hack, Sebastian ED - Eitzinger, Jan ED - Brodman, James T1 - A Data Layout Transformation for Vectorizing Compilers T2 - WPMVP'18: Proceedings of the 2018 4th Workshop on Programming Models for SIMD/Vector Processing UR - https://doi.org/10.1145/3178433.3178440 KW - Vectorization KW - Compiler KW - Optimization Y1 - 2018 UR - https://doi.org/10.1145/3178433.3178440 SN - 978-1-4503-5646-6 PB - ACM CY - New York ER - TY - JOUR A1 - Schuler, Manuela A1 - Membarth, Richard A1 - Slusallek, Philipp T1 - XEngine: Optimal Tensor Rematerialization for Neural Networks in Heterogeneous Environments JF - ACM Transactions on Architecture and Code Optimization N2 - Memory efficiency is crucial in training deep learning networks on resource-restricted devices. During backpropagation, forward tensors are used to calculate gradients. Despite the option of keeping those dependencies in memory until they are reused in backpropagation, some forward tensors can be discarded and recomputed later from saved tensors, so-called checkpoints. This allows, in particular, for resource-constrained heterogeneous environments to make use of all available compute devices. Unfortunately, the definition of these checkpoints is a non-trivial problem and poses a challenge to the programmer—improper or excessive recomputations negate the benefit of checkpointing. In this article, we present XEngine, an approach that schedules network operators to heterogeneous devices in low memory environments by determining checkpoints and recomputations of tensors. Our approach selects suitable resources per timestep and operator and optimizes the end-to-end time for neural networks taking the memory limitation of each device into account. For this, we formulate a mixed-integer quadratic program (MIQP) to schedule operators of deep learning networks on heterogeneous systems. We compare our MIQP solver XEngine against Checkmate [12], a mixed-integer linear programming (MILP) approach that solves recomputation on a single device. Our solver finds solutions that are up to 22.5% faster than the fastest Checkmate schedule in which the network is computed exclusively on a single device. We also find valid schedules for networks making use of both central processing units and graphics processing units if memory limitations do not allow scheduling exclusively to the graphics processing unit. UR - https://doi.org/10.1145/3568956 KW - rematerialization KW - integer linear programming KW - neural networks KW - memory management KW - heterogeneous computing Y1 - 2022 UR - https://doi.org/10.1145/3568956 UR - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:573-29989 SN - 1544-3973 VL - 20 IS - 1 PB - ACM CY - New York ER - TY - CHAP A1 - Kenzel, Michael A1 - Lemme, Stefan A1 - Membarth, Richard A1 - Kurtenacker, Matthias A1 - Devillers, Hugo A1 - Steinberger, Markus A1 - Slusallek, Philipp T1 - AnyQ: An Evaluation Framework for Massively-Parallel Queue Algorithms T2 - Proceedings: 2023 IEEE International Parallel and Distributed Processing Symposium: IPDPS 2023 UR - https://doi.org/10.1109/IPDPS54959.2023.00079 KW - Massively Parallel KW - Concurrent Queue KW - GPU Y1 - 2023 UR - https://doi.org/10.1109/IPDPS54959.2023.00079 SN - 979-8-3503-3766-2 SP - 736 EP - 745 PB - IEEE CY - Piscataway ER - TY - JOUR A1 - Xu, Xiang A1 - Wang, Lu A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Li, Cuiyu A1 - Yang, Chenglei A1 - Slusallek, Philipp T1 - Temporal Coherence-Based Distributed Ray Tracing of Massive Scenes JF - IEEE Transactions on Visualization and Computer Graphics UR - https://doi.org/10.1109/TVCG.2022.3219982 KW - Computer Graphics KW - Ray Tracing KW - Distributed Graphics Y1 - 2022 UR - https://doi.org/10.1109/TVCG.2022.3219982 SN - 1941-0506 SN - 1077-2626 VL - 30 IS - 2 SP - 1489 EP - 1501 PB - IEEE CY - Piscataway ER - TY - INPR A1 - Ravedutti Lucio Machado, Rafael A1 - Schmitt, Jonas A1 - Eibl, Sebastian A1 - Eitzinger, Jan A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Köstler, Harald T1 - tinyMD: A Portable and Scalable Implementation for Pairwise Interactions Simulations UR - https://doi.org/10.48550/arXiv.2009.07400 Y1 - 2020 UR - https://doi.org/10.48550/arXiv.2009.07400 PB - arXiv CY - Ithaca ER - TY - JOUR A1 - Xu, Wenguang A1 - Membarth, Richard T1 - Exploration of Efficient Computation for Trajectory Planning via Fixed-Point Arithmetic JF - PARS-Mitteilungen 2025 Y1 - 2025 UR - https://dl.gi.de/items/6b2c0546-1081-40ab-b97b-052b60b8374f SN - 0177-0454 VL - 37 SP - 51 EP - 61 PB - Gesellschaft für Informatik CY - Bonn ER - TY - JOUR A1 - Pfaller, Tobias A1 - Membarth, Richard T1 - Exploiting Data Redundancy in Im2Col Convolutions JF - PARS-Mitteilungen 2025 Y1 - 2025 UR - https://dl.gi.de/items/156c727e-ec90-4809-9ce6-ee27cc89eeb0 SN - 0177-0454 VL - 37 SP - 63 EP - 70 PB - Gesellschaft für Informatik CY - Bonn ER - TY - CHAP A1 - Sánchez Morales, Eduardo A1 - Membarth, Richard A1 - Gaull, Andreas A1 - Slusallek, Philipp A1 - Dirndorfer, Tobias A1 - Kammenhuber, Alexander A1 - Lauer, Christoph A1 - Botsch, Michael T1 - Parallel Multi-Hypothesis Algorithm for Criticality Estimation in Traffic and Collision Avoidance T2 - 2019 IEEE Intelligent Vehicles Symposium (IV) UR - https://doi.org/10.1109/IVS.2019.8814015 Y1 - 2019 UR - https://doi.org/10.1109/IVS.2019.8814015 SN - 978-1-7281-0560-4 SP - 2164 EP - 2171 PB - IEEE CY - Piscataway ER - TY - INPR A1 - Sánchez Morales, Eduardo A1 - Membarth, Richard A1 - Gaull, Andreas A1 - Slusallek, Philipp A1 - Dirndorfer, Tobias A1 - Kammenhuber, Alexander A1 - Lauer, Christoph A1 - Botsch, Michael T1 - Parallel Multi-Hypothesis Algorithm for Criticality Estimation in Traffic and Collision Avoidance UR - https://doi.org/10.48550/arXiv.2005.06773 Y1 - 2020 UR - https://doi.org/10.48550/arXiv.2005.06773 PB - arXiv CY - Ithaca ER -