TY - INPR A1 - Ravedutti Lucio Machado, Rafael A1 - Schmitt, Jonas A1 - Eibl, Sebastian A1 - Eitzinger, Jan A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Köstler, Harald T1 - tinyMD: A Portable and Scalable Implementation for Pairwise Interactions Simulations UR - https://doi.org/10.48550/arXiv.2009.07400 Y1 - 2020 UR - https://doi.org/10.48550/arXiv.2009.07400 PB - arXiv CY - Ithaca ER - TY - CHAP A1 - Müller, André A1 - Schmidt, Bertil A1 - Membarth, Richard A1 - Leißa, Roland A1 - Hack, Sebastian T1 - AnySeq/GPU: A Novel Approach for Faster Sequence Alignment on GPUs T2 - Proceedings of the 36th ACM International Conference on Supercomputing (ICS-2022) UR - https://doi.org/10.1145/3524059.3532376 Y1 - 2022 UR - https://doi.org/10.1145/3524059.3532376 SN - 978-1-4503-9281-5 PB - ACM CY - New York ER - TY - CHAP A1 - Amiri, Puya A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Leißa, Roland A1 - Hack, Sebastian T1 - FLOWER: a Comprehensive Dataflow Compiler for High-Level Synthesis T2 - Proceedings of the 2021 International Conference on Field-Programmable Technology (ICFPT) UR - https://doi.org/10.1109/ICFPT52863.2021.9609930 KW - high-level synthesis KW - dataflow KW - compiler KW - FPGA KW - transformations KW - high-performance computing Y1 - 2021 UR - https://doi.org/10.1109/ICFPT52863.2021.9609930 SN - 978-1-6654-2010-5 PB - IEEE CY - Piscataway (NJ) ER - TY - JOUR A1 - Özkan, M. Akif A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Teich, Jürgen A1 - Hannig, Frank T1 - AnyHLS: High-Level Synthesis with Partial Evaluation JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ITCSDI) UR - https://doi.org/10.1109/TCAD.2020.3012172 KW - Field programmable gate arrays KW - functional programming KW - high level synthesis KW - image processing Y1 - 2020 UR - https://doi.org/10.1109/TCAD.2020.3012172 SN - 1937-4151 VL - 39 IS - 11 SP - 3202 EP - 3214 PB - IEEE CY - New York ER - TY - CHAP A1 - Müller, André A1 - Schmidt, Bertil A1 - Hildebrandt, Andreas A1 - Membarth, Richard A1 - Leißa, Roland A1 - Kruse, Matthis A1 - Hack, Sebastian T1 - AnySeq: A High Performance Sequence Alignment Library based on Partial Evaluation T2 - Proceedings: 2020 IEEE 34th International Parallel and Distributed Processing Symposium (IPDPS 2020) UR - https://doi.org/10.1109/IPDPS47924.2020.00109 KW - Libraries KW - Computer architecture KW - Generators KW - Bioinformatics KW - Hardware KW - Field programmable gate arrays KW - Two dimensional displays Y1 - 2020 UR - https://doi.org/10.1109/IPDPS47924.2020.00109 SN - 978-1-7281-6876-0 SN - 1530-2075 SP - 1030 EP - 1040 PB - IEEE CY - Los Alamitos ER - TY - JOUR A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Slusallek, Philipp T1 - Rodent: Generating Renderers without Writing a Generator JF - ACM Transactions on Graphics (TOG) UR - https://doi.org/10.1145/3306346.3322955 KW - Rendering KW - Ray-tracing KW - Generator KW - Partial Evaluation Y1 - 2019 UR - https://doi.org/10.1145/3306346.3322955 SN - 1557-7368 SN - 0730-0301 VL - 38 IS - 4 PB - ACM CY - New York ER - TY - JOUR A1 - Leißa, Roland A1 - Boesche, Klaas A1 - Hack, Sebastian A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Müller, André A1 - Schmidt, Bertil T1 - AnyDSL: a partial evaluation framework for programming high-performance libraries JF - Proceedings of the ACM on Programming Languages N2 - This paper advocates programming high-performance code using partial evaluation. We present a clean-slate programming system with a simple, annotation-based, online partial evaluator that operates on a CPS-style intermediate representation. Our system exposes code generation for accelerators (vectorization/parallelization for CPUs and GPUs) via compiler-known higher-order functions that can be subjected to partial evaluation. This way, generic implementations can be instantiated with target-specific code at compile time. In our experimental evaluation we present three extensive case studies from image processing, ray tracing, and genome sequence alignment. We demonstrate that using partial evaluation, we obtain high-performance implementations for CPUs and GPUs from one language and one code base in a generic way. The performance of our codes is mostly within 10%, often closer to the performance of multi man-year, industry-grade, manually-optimized expert codes that are considered to be among the top contenders in their fields. UR - https://doi.org/10.1145/3276489 KW - partial evaluation KW - high-performance KW - parallelization KW - vectorization KW - GPU computing KW - library design Y1 - 2018 UR - https://doi.org/10.1145/3276489 UR - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:573-28104 SN - 2475-1421 VL - 2 IS - OOPSLA PB - ACM CY - New York ER - TY - CHAP A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Moll, Simon A1 - Leißa, Roland A1 - Hack, Sebastian ED - Eitzinger, Jan ED - Brodman, James T1 - A Data Layout Transformation for Vectorizing Compilers T2 - WPMVP'18: Proceedings of the 2018 4th Workshop on Programming Models for SIMD/Vector Processing UR - https://doi.org/10.1145/3178433.3178440 KW - Vectorization KW - Compiler KW - Optimization Y1 - 2018 UR - https://doi.org/10.1145/3178433.3178440 SN - 978-1-4503-5646-6 PB - ACM CY - New York ER -