TY - JOUR A1 - Özkan, M. Akif A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Leißa, Roland A1 - Hack, Sebastian A1 - Teich, Jürgen A1 - Hannig, Frank T1 - AnyHLS: High-Level Synthesis with Partial Evaluation JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ITCSDI) UR - https://doi.org/10.1109/TCAD.2020.3012172 KW - Field programmable gate arrays KW - functional programming KW - high level synthesis KW - image processing Y1 - 2020 UR - https://doi.org/10.1109/TCAD.2020.3012172 SN - 1937-4151 VL - 39 IS - 11 SP - 3202 EP - 3214 PB - IEEE CY - New York ER - TY - CHAP A1 - Özkan, M. Akif A1 - Pérard-Gayot, Arsène A1 - Membarth, Richard A1 - Slusallek, Philipp A1 - Teich, Jürgen A1 - Hannig, Frank T1 - A Journey into DSL Design using Generative Programming BT - FPGA Mapping of Image Border Handling through Refinement T2 - Fifth International Workshop on FPGAs for Software Programmers (FSP 2018) Y1 - 2018 UR - https://www.vde-verlag.de/proceedings-de/564723009.html SN - 978-3-8007-4723-8 SP - 64 EP - 72 PB - VDE Verlag CY - Berlin ER -