@article{OezkanPerardGayotMembarthetal.2020, author = {{\"O}zkan, M. Akif and P{\´e}rard-Gayot, Ars{\`e}ne and Membarth, Richard and Slusallek, Philipp and Leißa, Roland and Hack, Sebastian and Teich, J{\"u}rgen and Hannig, Frank}, title = {AnyHLS: High-Level Synthesis with Partial Evaluation}, volume = {39}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ITCSDI)}, number = {11}, publisher = {IEEE}, address = {New York}, issn = {1937-4151}, doi = {https://doi.org/10.1109/TCAD.2020.3012172}, pages = {3202 -- 3214}, year = {2020}, language = {en} } @inproceedings{OezkanPerardGayotMembarthetal.2018, author = {{\"O}zkan, M. Akif and P{\´e}rard-Gayot, Ars{\`e}ne and Membarth, Richard and Slusallek, Philipp and Teich, J{\"u}rgen and Hannig, Frank}, title = {A Journey into DSL Design using Generative Programming}, booktitle = {Fifth International Workshop on FPGAs for Software Programmers (FSP 2018)}, subtitle = {FPGA Mapping of Image Border Handling through Refinement}, publisher = {VDE Verlag}, address = {Berlin}, isbn = {978-3-8007-4723-8}, url = {https://www.vde-verlag.de/proceedings-de/564723009.html}, pages = {64 -- 72}, year = {2018}, language = {en} }