TY - JOUR A1 - Endres, Julian A1 - Haas, Tobias A1 - Pawellek, Alexander A1 - Kremer, Vinicius A1 - Franchino, Roger T1 - Evaluation of GaN Transistors for Grid-Connected 3-Level T-Type Inverters JF - Electronics N2 - This paper presents a complete workflow for the evaluation of GaN transistors in voltage source inverters. With the associated high switching speed of transistors based on GaN, it is important to consider some critical points in the design phase as well as in the measurement setup in order to be able to utilise and verify the advantages of GaN properly. For this reason, the presented circuit board’s design focuses on a minimised power loop inductance. Simulation models, an analytical approach and measurement results with the aim of determining this inductance are compared with each other. A good compliance results between the presented methods. Additionally, the description of a test bench is given, which enables the performance of the opposition method. This setup allows the measurement of the designed H-bridge’s arising losses and the GaN-transistor’s switching behaviour. In comparison to the conventional double pulse method, this approach enables results that are more accurate for determining losses. Y1 - 2025 U6 - https://doi.org/https://doi.org/10.3390/electronics14152935 SN - 2079-9292 VL - 14 IS - 15 PB - MDPI ER -