85.40.-e Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology (see also 85.45.-w Vacuum microelectronics); Microwave integrated electronics, see 84.40.Lj; Integrated optics, see 42.82.-m; Superconducting logic elements and memory devices; m
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- 2010 (1)
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- Doctoral Thesis (1)
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- Computersimulation (1)
- Gattersimulation (1)
- Kontaktwiderstände (1)
- Logiksimulation (1)
- MOS-FET (1)
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- SPICE <Programm> (1)
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A full device simulation study of MOSFETs up to the circuit level is presented in this thesis. Bulk MOSFETs, single gate fully depleted silicon on insulator (SG FDSOI) MOSFETs, double gate fully depleted silicon on insulator (DG FDSOI) MOSFETS, and triple gate (TG) FinFETs below 50 nm gate lengths were investigated by means of TCAD and SPICE simulations. A novel charge carrier transport model is presented in order to take quasi-ballistic charge carrier transport into account in conventional Drift-Diffusion simulations. Process options for improving the electrical MOSFET behavior by means of mechanical stress are discussed. A modified piezo model for taking saturation of hole mobility enhancement at high mechanical stress values into account is presented. The impact of Schottky contact resistances on the electrical behavior of MOSFET devices at decreasing device dimensions is investigated by means of process simulations, device simulations, and measurements. Suggestions for efficiently reducing contact resistances are made and demonstrated by process and device simulations. Classical and alternative MOSFET architectures are investigated and compared by numerical process and device simulation concerning their suitability for fulfilling the requirements of high performance (HP) devices, low operating power (LOP) devices, and low standby power (LSTP) devices of the 32 nm technology node of the International Technology Roadmap for Semiconductors (ITRS). Several process options were used to improve the MOSFET behavior to achieve Ion-Ioff and CV/I requirements demanded by the ITRS. SPICE parameters of LSTP bulk and SOI MOSFETs were extracted using classical bulk MOSFET compact models. A method of efficient multi-gate compact modeling using classical bulk compact models is presented. DG FDSOI, and TG FinFET transistors were modeled using extended compact modeling. Circuit simulations of an inverter, 7 stage ring oscillator, 4-bit ripple carry adder, and 6-transistor static random access memory (6-T SRAM) cell were performed using classical and alternative MOSFET architectures. The different behavior of bulk MOSFETs, SG FDSOI MOSFETs, DG FDSOI MOSFETs, and TG FinFET transistors under integrated circuit conditions is discussed. Finally, the impact of process variations on the electrical performance of classical and alternative MOSFET architectures is demonstrated. Lithography simulations were coupled to process and device simulations to investigate the impact of lithography parameter fluctuations on the physical gate length and the final MOSFET behavior. A SPICE parameter extension is presented to take the impact of four different process variations into account in SPICE simulations. The impact of gate length fluctuations, body thickness fluctuations, flash annealing peak temperature fluctuations, and dose fluctuations of source/drain region implantation were modeled using SPICE simulations. Additionally, threshold voltage fluctuations due to random discrete dopants (RDD) were taken into account in SPICE simulations in case of bulk MOSFETs. Finally, the impact of process variations on integrated circuits is discussed. Classical and alternative MOSFET architectures based integrated circuits were investigated concerning their stability against process variations.