85.30.Tv Field effect devices
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The present work addresses the characterization and the optimization of the interface between 4H-SiC (Silicon Carbide) and SiO2 (Silicon Dioxide) for applications in power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The first part focuses on the characterization and development of different gate oxidation processes for an improved channel mobility. The gate oxides investigated in this thesis were realized with different methods, either by thermally growing or by depositing an oxide layer which was subsequently post-oxidized in dry oxygen (O2), nitrous oxide (N2O) or nitric oxide (NO) gases. The results of these experiments are discussed in the light of the current understanding of SiC interface passivation and nitridation. In particular, the dependence on time and temperature of the nitridation process in NO of deposited oxides is highlighted and its effect is for the first time studied with the help of regression analysis of wafer-scale measurements on MOS capacitors. It is found that the nitridation in NO gas leads to the best interface passivation, especially for longer times and higher temperatures of the treatment, confirming the existing models. On MOSFETs with optimized gate oxides, the effect of the interface states density on the transistor’s performance has also been studied in a large temperature range. The results suggest that the mobility is a thermally activated process in the presence of a high concentration of interface defects, in strong contrast to Si MOSFETs. This behavior – typical of amorphous semiconductors – might indicate that a disordered layer exist at the interface, as suggested by some research groups. In order to verify this hypothesis, a deeper look at the SiC/SiO2 interface is given by the HRTEM and EDX analysis of the fabricated samples, in order to shed some light on its nature. This complements the electrical measurements and allows to study the microscopic structure of SiC/SiO2 interface. No signs of an interlayer if amorphous nature or presence of carbon clusters are visible from this analysis, in contrast to previous reports. Furthermore, the properties of theMOS interface fabricated on in-situ Germanium (Ge)-doped epitaxial layers are presented, as a novel approach for the reduction of the interface defect density. A second target of this work is the comparison of the MOS interface characterization methods coming from the Si world. In particular, the techniques based on impedance measurements on MOS capacitors – High-Low Frequency Capacitance and Conductance methods – could in some cases underestimate the real interface states density. Among the methods based on MOSFETs, the Charge Pumping technique has been successfully transferred from Si to SiC transistors and it was possible to extract the interface states profile over bandgap energy, for the first time on SiC transistors. Moreover, the Charge Pumping method presents a larger accuracy on MOSFETs with respect to that achievable with techniques based on MOS capacitors, especially when characterizing optimized gate oxides with a low concentration of interface states.
Part of 15th International Workshop on Radiation Imaging Detectors (IWORID2013)
A photon counting, microchannel plate (MCP) optical imaging tube has been fabricated using a 2 × 2 array of Timepix application specific integrated circuits (ASICs) as the readout anode. A Timepix ASIC is a 256 × 256 pixellated CMOS readout chip with each pixel containing an amplifier, discriminator and counter. The counter values, representing either time of arrival, total count or time over threshold, can record the position and time of arrival of the electron pulses from the MCP if the charge collected on its input pads exceed the adjustable lower threshold value. Below we present initial results of the tube's performance, the quantum efficiency of the bi-alkali photocathode, uniformity of response, spatial and temporal resolution, and dynamic range. Planned improvement to the design based on the new Timepix3 chip will be discussed.
Due to the lack of graphene transistors with large on/off ratio, we propose a concept employing both epitaxial graphene and its underlying substrate silicon carbide (SiC) as electronic materials. We demonstrate a simple, robust, and scalable transistor, in which graphene serves as electrodes and SiC as a semiconducting channel. The common interface has to be chosen such that it provides favorable charge injection. The insulator and gate functionality is realized by an ionic liquid gate for convenience but could be taken over by a solid gate stack. On/off ratios exceeding 44000 at room temperature are found.
In this work, we report on the electronic properties of solution-gated field effect transistors (SGFETs) fabricated using large-area graphene. Devices prepared both with epitaxially grown graphene on SiC as well as with chemical vapor deposition grown graphene on Cu exhibit high transconductances, which are a consequence of the high mobility of charge carriers in graphene and the large capacitance at the graphene/water interface. The performance of graphene SGFETs, in terms of gate sensitivity, is compared to other SGFET technologies and found to be clearly superior, confirming the potential of graphene SGFETs for sensing applications in electrolytic environments.
Three different ultrathin hybrid dielectrics based on self-assembled monolayers (SAMs) from phosphonic acid molecules were investigated on aluminum oxide. The impact of the underlying SAMs on the semiconductor morphology and transistor device performance was studied by reducing the film thickness of the subsequently deposited α,ω-dihexylquaterthiophene semiconductor to one monolayer and less. The nature of the SAM relates to the molecular orientation of submonolayer films, which is investigated by photoluminescence microscopy and atomic force microscopy. SAMs with high surface energy tend to induce a face-on growing of the semiconductor, whereas for SAMs with low surface energy an edge-on growth is favorable.
Germanium war in den fünfziger und sechziger Jahren des letzten Jahrhunderts in der Halbleiterindustrie ein dominierender Werkstoff, wurde aber bald durch Silicium abgelöst. Die Gründe dafür waren, die aus der höheren Bandlücke des Siliciums resultierenden geringeren Leckströmen in Bauelementen sowie die hervorragenden Eigenschaft des Siliciumoxids als Passivierung und Isolatormaterial für den Bau von MOSFETs (Feldeffekttransistoren mit isolierter Steuerelektrode). Da in hochintegrierten Schaltungen jedoch die notwendige Dicke des Gatedielektrikums unter der Steuerelektrode immer weiter abnimmt, steigen als Folge Leckströme durch den Isolator immer weiter an. Das führt zur Einführung alternativer Isolatormaterialien, womit die Eigenschaften des SiO2 als Vorteil des Siliciums nicht mehr gelten. Damit steigt das Interesse an Germanium als alternativen Halbleiter, da man sich einen verbesserten Stromtransport durch hohe Beweglichkeiten in integrierten MOSFETs verspricht. Aufgrund der geringen Verfügbarkeit ist jedoch zu erwarten, dass Germanium nur in Form dünner Schichten auf Siliciumsubstraten eingesetzt wird. Bevorzugt werden dabei GeOI-Substrate (engl. GErmanium-On-Insulator, dt. Germanium auf Isolator). Im Rahmen dieser Arbeit wird die Integration von MOSFETs in Germaniumschichten untersucht. Es werden verschiedene Einzelprozessschritte betrachtet und ihre spezifischen Eigenschaften beim Einsatz für Germanium untersucht. Bei der Prozessführung ist zu vermeiden, dass eine blanke Germaniumfläche bei hohen Temperaturen mit der umliegenden Atmosphäre wechselwirken kann. Es werden Ätzgruben und Substratverlust von bis zu 3 nm/min bei 600 °C aufgrund von Kleinstmengen von Sauerstoff in nominell inerten Atmosphären (Ar, N2 oder Vakuum) beobachtet. Eine Verringerung dieses Effektes ist durch niedrigere Temperaturen, kleine Ofenvolumina, Vakuumbedingungen und Deckschichten zu erreichen. Für die Dotierung wird vorzugsweise die Ionenimplantation genutzt. Bei Germanium treten Oberflächenrauigkeiten oder vergrabene Hohlräume bei der Implantation schwerer Ionen wie Ga, As oder Sb oberhalb einer kritischen Dosis auf, die für alle drei Elemente bestimmt wird. Die Ergebnisse sprechen gegen einen Einfluss der Implantationsenergie auf die kritische Dosis. Als Bildungsmechanismus kann reines Sputtern ausgeschlossen werden. Als eine potentielle Passivierungsmethode wird die Verwendung von Germaniumoxid untersucht, da hier geringe Grenzflächenzustandsdichten zu erwarten sind. Dazu wird die Oxidation betrachtet. Bei Germanium tritt neben dem Oxidwachstum ein Mechanismus hinzu, der die Oxiddicke verringert und höhere Grenzflächenzustände verursacht. Um die Degradation im Prozess zu verringern, sollte unter Sauerstoffatmosphäre abgekühlt werden. Zur Demonstration einer möglichen Technologie wird ein Prozess für den Bau von MOSFETs auf Germaniumsubstrat dargestellt. Als mögliches hoch-epsilon Dielektrikum wird Al2O3 untersucht. Die thermische Stabilität von Schichtstapeln aus GeO2 und Al2O3 bei Ausheilungen in Formiergas wird untersucht. Dazu werden MOS-Kondensatoren mit Elektroden aus Al oder Ti hergestellt. Es zeigt sich eine Zerstörung der Stapel oberhalb von 450 °C bei Aluminiummetallisierung und oberhalb von 375 °C bei Titanmetallisierung. Bis zu dieser Grenztemperatur wird für Schichtstapel mit einer Aluminiummetallisierung eine Reduktion der Grenzflächenzustandsdichte, der Summe der Oxidladungen und der Flachbandhysterese festgestellt. Mit diesem Stapel wird ein p-Kanal MOSFET mit einer effektiven Kanalbeweglichkeit von maximal 315 cm²/Vs demonstriert. Dagegen wirkt sich eine Titanmetallisierung nachteilig auf die Beweglichkeit aus und es wird lediglich eine Kanalbeweglichkeit von 13,9 ± 1,5 cm²/Vs erreicht. Für die Wahl des Gatemetalls ist daher eine potentielle Wechselwirkung mit dem Gatedielektrikum zu berücksichtigen.
A full device simulation study of MOSFETs up to the circuit level is presented in this thesis. Bulk MOSFETs, single gate fully depleted silicon on insulator (SG FDSOI) MOSFETs, double gate fully depleted silicon on insulator (DG FDSOI) MOSFETS, and triple gate (TG) FinFETs below 50 nm gate lengths were investigated by means of TCAD and SPICE simulations. A novel charge carrier transport model is presented in order to take quasi-ballistic charge carrier transport into account in conventional Drift-Diffusion simulations. Process options for improving the electrical MOSFET behavior by means of mechanical stress are discussed. A modified piezo model for taking saturation of hole mobility enhancement at high mechanical stress values into account is presented. The impact of Schottky contact resistances on the electrical behavior of MOSFET devices at decreasing device dimensions is investigated by means of process simulations, device simulations, and measurements. Suggestions for efficiently reducing contact resistances are made and demonstrated by process and device simulations. Classical and alternative MOSFET architectures are investigated and compared by numerical process and device simulation concerning their suitability for fulfilling the requirements of high performance (HP) devices, low operating power (LOP) devices, and low standby power (LSTP) devices of the 32 nm technology node of the International Technology Roadmap for Semiconductors (ITRS). Several process options were used to improve the MOSFET behavior to achieve Ion-Ioff and CV/I requirements demanded by the ITRS. SPICE parameters of LSTP bulk and SOI MOSFETs were extracted using classical bulk MOSFET compact models. A method of efficient multi-gate compact modeling using classical bulk compact models is presented. DG FDSOI, and TG FinFET transistors were modeled using extended compact modeling. Circuit simulations of an inverter, 7 stage ring oscillator, 4-bit ripple carry adder, and 6-transistor static random access memory (6-T SRAM) cell were performed using classical and alternative MOSFET architectures. The different behavior of bulk MOSFETs, SG FDSOI MOSFETs, DG FDSOI MOSFETs, and TG FinFET transistors under integrated circuit conditions is discussed. Finally, the impact of process variations on the electrical performance of classical and alternative MOSFET architectures is demonstrated. Lithography simulations were coupled to process and device simulations to investigate the impact of lithography parameter fluctuations on the physical gate length and the final MOSFET behavior. A SPICE parameter extension is presented to take the impact of four different process variations into account in SPICE simulations. The impact of gate length fluctuations, body thickness fluctuations, flash annealing peak temperature fluctuations, and dose fluctuations of source/drain region implantation were modeled using SPICE simulations. Additionally, threshold voltage fluctuations due to random discrete dopants (RDD) were taken into account in SPICE simulations in case of bulk MOSFETs. Finally, the impact of process variations on integrated circuits is discussed. Classical and alternative MOSFET architectures based integrated circuits were investigated concerning their stability against process variations.