85.30.De Semiconductor-device characterization, design, and modeling
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In this work, we analyze electrically the Al/p-Si/[6,6] phenyl-C61 butyric acid methyl ester/Al hybrid heterojunction. The barrier height at the p-Si/PCBM interface corresponding to the difference between Si valence band edge and the lowest unoccupied molecular orbital energy level of PCBM is studied with current-voltage (J-V) and capacitance-voltage (C-V) methods and determined to be ≃ 0.55 eV. This value is in agreement with the onset energy of spectrally resolved photocurrent measurements presented in a previous publication [Matt et al., Adv. Mater. 22, 647 (2010)]. For the J-V characteristics, a thorough model based on an interface generation-recombination current is proposed. All relevant energy levels for this model are obtained experimentally. As origin of the large reverse current, the thermal generation of charge carriers throughout the Si depletion region is identified by the thermal activation measurements.
Continuous scaling down of semiconductor device dimensions has been key to the semiconductor industry being able to deliver better performing electronics at reduced costs. At the time of writing, CMOS manufacturing technology is at the 32 nm node, which requires an SiO2 gate insulation thickness of less than 1 nm. At such thicknesses, the direct tunneling gate leakage current is extremely high, leading to high power consumption. To overcome this problem, industry consensus has been to replace SiO2 by high permittivity (high-k) dielectrics. Hafnium-based high-k dielectrics are favored for this substitution. The conventional polysilicon gate has also been replaced by a metal gate in order to eliminate the parasitic effect of charge depletion at the polysilicon/high-k interface. This novel gate stack is, however, not stable to high temperature (1000°C) anneals used in semiconductor processing. A major difficulty is the change in the transistor threshold voltage after source/drain anneals, which implies a shift of the effective work function (EWF) of the gate electrode. The threshold voltage increases both for NMOS and PMOS devices. In this work, it is shown that by doping metal/high-k transistor gate stacks by ion implantation the EWF can be controlled. This allows the use of a single metal for both PMOS and NMOS devices in a gate-first integration scheme. A fluorine-doped TiN/HfSiOx or TiN/HfO2 gate stack achieves an EWF of about 5.1 eV for PMOS devices. For NMOS devices, lanthanum-doped TiN/HfSiOx gate stacks achieve an EWF of about 4.0 eV.