A Chip-Area-Efficient Baseband Processing Core for FMCW Radar-based Sensor Network Localization

Chipflächeneffzienter Basisbandverarbeitungskern für FMCW-Radar-basierte Lokalisierung in Sensornetzwerken

Please always quote using this URN: urn:nbn:de:bvb:29-opus4-57617
  • There exists a variety of industrial applications in local environments, with an increasing demand for low-power and high-precision local positioning solutions based on wireless sensor networks. The focus of developing autonomous and cooperative sensor nodes with localization functionality is on the localization accuracy and range, energy efficiency and the size of the sensor nodes. In this context special attention is paid to the sensor digital signal processing, where the main task is to perform a Fast Fourier Transform (FFT). In this work the design of the radix-4 DIF FFT algorithm and its optimization with respect to hardware implementation for low-power local positioning systems isThere exists a variety of industrial applications in local environments, with an increasing demand for low-power and high-precision local positioning solutions based on wireless sensor networks. The focus of developing autonomous and cooperative sensor nodes with localization functionality is on the localization accuracy and range, energy efficiency and the size of the sensor nodes. In this context special attention is paid to the sensor digital signal processing, where the main task is to perform a Fast Fourier Transform (FFT). In this work the design of the radix-4 DIF FFT algorithm and its optimization with respect to hardware implementation for low-power local positioning systems is introduced. Furthermore, an area-efficient digital implementation of a baseband processing core for autonomous wireless sensor nodes with localization functionality is presented. The challenge for designing the digital system was to reduce memory requirements towards a low cost hardware design in general, and particularly for an ASIC design. Reducing chip area implies lower energy consumption and helps saving implementation and production costs. The presented novel baseband processing system concept has been implemented and verified on an FPGA. For the application scenario of a two-sweep-measurement system, an ASIC layout is designed based on the IBM 130 nm CMOS technology.show moreshow less

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Metadaten
Author:Alban Ferizi
URN:urn:nbn:de:bvb:29-opus4-57617
ISBN:978-3-944057-27-9
Series (Volume number):FAU Studien aus der Elektrotechnik (2)
Publisher:FAU University Press
Place of publication:Erlangen
Referee:Robert Weigel, Armin Dekorsy
Document Type:Doctoral Thesis
Language:English
Year of Completion:2014
Publishing Institution:FAU University Press
Granting Institution:Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Technische Fakultät
Date of final exam:2014/11/28
Release Date:2015/01/21
Tag:ASIC; CMOS; Discrete Fourier Transform; FMCW radar; FPGA; Fast Fourier Transform; baseband signal processing; digital signal processing; industry automation; local positioning; microwave radio localization; radix-4; wireless sensor networks
SWD-Keyword:Diskrete Fourier-Transformation; Schnelle Fourier-Transformation; Digitale Signalverarbeitung
Pagenumber:xv, 130 S.
Note:
Parallel erschienen als Druckausgabe bei FAU University Press
Institutes:Technische Fakultät / Department Elektrotechnik-Elektronik-Informationstechnik
Dewey Decimal Classification:0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
open_access (DINI-Set):open_access
Collections:Universität Erlangen-Nürnberg / FAU University Press
Licence (German):Creative Commons - CC BY-NC-ND - Namensnennung - Nicht kommerziell - Keine Bearbeitungen 3.0