A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.


I. INTRODUCTION
Resistive Random Access Memory (RRAM) is an emerging Non-Volatile Memory (NVM) with increasing applications in memory and logic circuits [1], [2]. The fundamental device in RRAM is a Metal-Insulator-Metal structure which can store data as resistance of a conductive filament formed in the insulator [3]. The conductive filament can be grown (Low Resistance State (LRS)) and broken (High Resistance State (HRS)) under voltage stress, enabling writing and erasing of data. The quest to increase memory density has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. In RRAM, MLC is implemented by varying the compliance current, or by varying the voltage, or by varying the programming pulse widths [4]. Among these three methods, implementing MLC by varying the compliance current is the most viable method to implement MLC in RRAM [5]. The RRAM is integrated in series with a transistor and the compliance current is varied by varying the gate voltage of the transistor in a 1 Transistor-1 Resistor (1T1R) configuration. In this way, a single HRS and multiple LRS (corresponding to different compliance currents) are implemented and, the physical phenomenon is believed to be the formation and subsequent widening of the conductive filament with increasing compliance current ( Fig.1-(a)). Demonstration of MLC in RRAM by varying the compliance current can be found in [6]- [9] (read-out currents of some of these MLC RRAMs is listed in Table I).
To 'read' the data from a MLC RRAM, we need a sensing methodology to convert the resistance to a digital data, which is the focus of this paper. Based on the architecture, sensing methodology can be either sequential or parallel. In a sequential approach to MLC sensing, a single Sense Amplifier (SA) is used and numerous comparisons are made by varying the reference quantity (voltage or current) sequentially, resulting in the identification of the cell resistance [10]. The parallel approach uses numerous sense amplifiers and compares the read quantity with the reference quantity simultaneously, similar to a flash ADC. The former approach has less hardware complexity but incurs latency, while the latter achieves high speed sensing at the cost of hardware. From another perspective, the sensing methodology for resistive memories can be voltage-mode or current-mode. In voltage-mode sensing, the bit-line (BL) is pre-charged to a voltage and then the word-line (WL) is activated. Depending on the RRAM cell's resistance, the BL voltage changes (either marginally if HRS or drastically if LRS) and the change is captured by comparing with a reference voltage in voltagemode SA. In current-mode sensing, a small voltage is applied across the RRAM cell and the induced current is drawn out and compared with the reference current in a current-mode SA. A detailed review of both the schemes and the challenges faced in sensing can be found in [11]. All these sensing techniques need an absolute reference voltage/current for comparison and generating multiple references (V REF /I REF ) adds overhead to the sensing circuitry. In sequential sensing, the references have to be generated and also compared with the quantity to be sensed using a control circuit. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the memory cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The sensor delineates the states by the relative current magnitude and hence, does not require any reference current. The circuit and the simulations results are presented in the following section.  1µA 10µA 20µA 40µA 50µA 70µA 100µA 120µA [9] II. PROPOSED SENSING METHODOLOGY

A. Principle
In the first stage of sensing, the RRAM's resistance is converted to a current which flows in the N 1 -N 2 current mirror, following the approach of [12]. In a 1T-1R configuration, this is implemented by activating the WL and applying a small voltage (typically <= 0.2 V so that the cell's state is not disturbed) across the cell. As depicted in Fig.1-(b), the op-amp biases the drain of N 1 at a constant voltage, V BIAS to ensure that N 1 is in saturation (feedback bias [12]). Therefore, transistor pair N 1 −N 2 acts as a current-mirror and I read will be mirrored in N 2 and is available for sensing 1 . This I read is used to discharge the capacitor which is precharged to V DD (when SENSE ENABLE signal (EN) is low, the capacitor is charged through P 1 to V DD ). When EN goes high, sensing starts. The capacitor discharges from V DD at a rate proportional to I read . However, when the voltage at I ST goes below V T L , O ST goes low and stops the discharging process (N 4 is OFF). The capacitor at I ST starts charging (through P 2,3 ) till it reaches V T H . When I ST reaches V T H , O ST goes high and this triggers the discharging of I ST (N 4 is ON). This discharging and charging repeats as long as EN is high. This periodic discharging and charging of the capacitor results in a pulse train at O ST (a discharge followed by a charge constitutes a single negative pulse). Since the discharging time is proportional to I read , a higher current will generate more pulses. By carefully choosing the capacitor value and EN time period, currents of increasing magnitude can be converted to increasing number of pulses. The resulting pulses are then converted to bits using a synchronous binary counter clocked with the pulse train.

B. Circuit design and simulation results
In this section, we describe the design methodology of the sensing circuit of Fig. 1 in IHP's 130 nm CMOS technology (V DD = 1.2 V). The op-amp used to bias the current mirror is a classical two-stage miller-compensated op-amp. V BIAS of 0.8 V was used at the input of op-amp to bias the drain of N 1 . Since the SL is held at 0.8 V, 1 V was applied at the BL to read from the RRAM cell. When WL is activated, the voltage across the 1T1R cell (BL-SL) is 0.2 V and I read was 3/20/30/40 µA, depending on the programmed state (The RRAM was programmed to different states using the modified Stanford-PKU RRAM model presented in [5]). The drawn current is mirrored and N 2 will sink I read when connected to V DD . In this manner, the current to be sensed is separated from the memory array's influence (wire parasitic, array size etc) and the design of the sensing circuit is independent of the array size, enabling easy portability.
Above the N 2 transistor is a NAND-like CMOS structure which acts as the control circuit for the discharging and Throughout the MLC sensing phase, EN must be high. Even when EN is high, if O ST is low, the capacitor is allowed to charge (N 4 is OFF) through P 2,3 . It must be noted that the discharging time is the crucial time which determines the number of pulses. This is because the capacitor is discharged by I read , while it is charged (towards V DD ) at a constant time, independent of I read . This necessitates a relatively shorter charging time so as to make the total period of the pulse (discharging+ charging time) proportional to I read . The two PMOS transistors (P 2,3 ) serve this purpose and further, their (W/L) was made (450/130) nm to drastically shorten the charging time. All other transistors in Fig. 1 are sized normally, i.e (150/130) nm. This periodic discharging and charging of the capacitor at I ST is converted to a pulse train by the ST circuit. To minimize hardware, we chose the six-transistor ST circuit of [13]. This compact ST has a fixed V T L of 0.53 V and V T H of 0.76 V in 130 nm technology. The capacitor charges from 0.53 V to 0.76 V in approximately 1 ns, thereby producing a negative pulse of ns duration. Since the binary counter is clocked with this ns wide negative pulse, we need a Flip-flop (FF) which can operate with GHz clock. We chose the extended true single-phase clocked (E-TSPC) FF presented in [14] which is a negative edge-triggered FF capable of operating in GHz frequencies [15], [16].
The value of C and the EN time period (T EN ) must be determined judiciously, and, the following observations must be taken into account to ensure accurate sensing in-spite of variations in the RRAM's resistance/I read .
1) The spacing between I HRS and the first LRS, I LRS1 is greater than the spacing between neighboring LRS in most MLC RRAMs ( Fig. 1-(a)). Hence, the circuit can be designed to produce no pulse for HRS, while LRS1, LRS2 and LRS3 will produce one, two and three pulses, respectively.
2) The amount of RRAM variations tolerated by the sensing circuit will be maximum if the circuit is designed to switch from producing n pulse to n+1 pulse midway between two low resistance states. We shall describe the design of the proposed MLC sensing circuit to distinguish between the four states of the MLC RRAM manufactured at IHP. Therefore, the circuit must be designed to differentiate between 3 µA (HRS) and 20 µA, 30 µA and 40 µA (three LRS).
Since the current which discharges the capacitor C is a constant current, I read , the rate at which capacitor voltage decreases is a constant in a given sensing period, given by making the voltage across the capacitor When I read is 3 µA, C should not discharge below V T L of the ST for one EN period i.e not even a single negative pulse.
When I read is 40 µA, C should discharge and charge three times in one EN period, producing three negative pulses and T EN must be long enough to accommodate them.
where T dis/ch x−y is the time for the voltage across the capacitor to discharge/charge from voltage x to y. From Eq. 3, and the charging time 2 is given by, where R P M OS is the ON resistance of the P 2,3 . Therefore, for a given I read , Eq 4 and 5 can be used to derive C and T EN to satisfy them. Once the boundary conditions (3 µA and 40 µA) are satisfied, it can be verified that the intermediate states, 20 µA and 30 µA will produce one and two negative pulses, respectively. This is because, from Eq. 6, the discharging time is a strong function of I read (other parameters C,V T H ,V T L fixed) and currents less than 40 µA will have larger discharge time and consequently less pulses in the same period, T EN . To accommodate maximum RRAM variations, the derived C and T EN can be fine-tuned so that the circuit transitions from producing one pulse to two pulses around 25 µA, and from two pulses to three pulses around 35 µA. For IHP's MLC RRAM, C of 0.5 pF and T EN of 24 ns satisfy the requirements to sense the four states with maximum tolerance to variations. Simulation results are plotted in Fig. 2-(a-d).
Further, to investigate the tolerance to RRAM variations, I read was varied around the mean current of a state and the output is plotted in Fig. 2-(e,f). From fig. 2-(e,f), one can verify that the sensor tolerates I read ± 4 µA variations. This was achieved by carefully choosing C and T EN to transition from producing n to n + 1 pulse midway between neighboring I LRS i.e the sensing circuit was engineered to transition from one to two pulse approximately at 25 µA, and, from two to three pulse at 35 µA. The conversion of pulse train to bits by the binary counter was also verified by simulations.

A. Principle
The sensing circuit of Fig. 1 requires a pF capacitor which will be difficult to implement in CMOS -a precise pF capacitance is difficult to design and also occupies more area. Since the sensing circuit has to be area optimized, we replaced the passive capacitor of Fig. 1 with a MOSFET capacitance and redesigned the circuit as depicted in Fig. 3. Since the input capacitance of the MOSFET in 130 nm will be in fF, the current has to be scaled down accordingly to have a similar circuit operation. This is achieved in two stages: first, the magnitude of the read current is reduced by four by proportionately reducing the READ voltage applied across 2 derived from the observation that a capacitor initially charged to V ini charges towards V DD with the instantaneous voltage, Fig. 3. The sensing circuit proposed in Fig. 1 is modified by replacing it's passive capacitor with a MOSFET's gate capacitance N 5 . I read is reduced by reducing the voltage across the RRAM cell and further divided by 10 to achieve a small current which can discharge the f F capacitance of the MOSFET in ns time . the RRAM cell. This is accomplished by applying 0.85 V to the BL when using V BIAS of 0.8 V, resulting in only 50 mV across the cell (as opposed to 200 mV used in Fig. 1). For IHP's RRAM, this amounts to a read-out current of 0.75 µA (HRS), 5 µA (LRS1), 7.5 µA (LRS2) and 10 µA (LRS3) for the four states. Next, the resulting I read is further scaled by the N 1 -N 2 current mirror to I read 10 i.e ( W L ) N1 = 10 × ( W L ) N2 . With this current scaling, the capacitance at node I ST can be charged/discharged in ns duration so as to enable the pulses to be captured by the counter at the output of the ST.

B. Circuit design and simulation results
We shall design the circuit of Fig. 3 to sense IHP's MLC RRAM in 130 nm CMOS technology. The capacitance to be charged/discharged is the MOSFET's gate capacitance and hence fixed by the technology. We have little freedom to change the (W/L) and it is set to (1100/130) nm to get a higher capacitance. Therefore, C is fixed and T EN is the only parameter of Equations 4 and 5, which can be designed to sense a given I read . Another undesirable effect of the improved circuit is that the charging time is also considerably reduced due to the reduced capacitance at node I ST . Since the time to charge (from V T L to V T H ) determines the width of the negative pulse, the charging time must be long enough (hundreds of ps or a fraction of a ns) to produce a negative pulse wide enough to act as the clock of the counter. To achieve this, the ( W L ) P M OS was made 6 × ( W L ) N M OS in the Schmitt Trigger (Fig. 3). Such a sizing of the transistors increased the V T H of the ST, thereby producing a negative pulse of 0.25 ns duration. With the transistors sized as shown in Fig. 3, the circuit was able to produce three negative pulse for LRS3 and no pulse at all for HRS when T EN was 10 ns. Simulation results are plotted in Fig. 4: (a)-(d). Further, to investigate the tolerance to RRAM variations, I read was varied around the mean current of a state and the output is plotted in Fig. 4: (e,f). The circuit is able to tolerate ± 0.75 µA around the mean current of the state.

C. Significance of results
The tolerance to RRAM's variations is reduced in the MOS capacitor circuit i.e ± 0.75 µA as opposed to ± 4 µA. This  is because the margin between neighboring LRS states is reduced to 2.5 µA and EN time period is also less, producing closely spaced pulses (Fig.4). However, a tolerance of ± 0.75 µA is still reasonable since the spacing between neighbouring LRS states is only 2.5 µA. In Table II, the variations in the programmed resistive state is expressed as a percentage of the mean resistance of the state and analyzed for each state. The tolerance % is different for each LRS because the same current tolerance (± 0.75 µA) translates as different resistance tolerance since the mean resistance is different. Therefore, the proposed sensing methodology can tolerate 13.1% variations at LRS1 while only 7% variations at LRS3. Interestingly, this reduced tolerance at lower resistances is not a disadvantage in RRAM technology since, the lower the resistance of RRAM cell, less the variations it exhibits. This is because at lower resistance (which is achieved by using a higher compliance current), the increased number of oxygen vacancy defects present in the filament form a well-defined conductive path, thereby exhibiting less variation [4]. For example, for a T iN/T i/Hf O x /T iN MLC RRAM studied in [17], the variation at LRS1, LRS2 and LRS3 are 12.6%, 3.2% and 2.4 % respectively. For the same device, the variation at HRS is 20.5% and the higher variation at HRS in RRAM technology is attributed to the stochastic nature of filament rupture [18]. In the proposed sensing method, we are able to accommodate the increased variation at HRS (upto 62%) because we assigned the HRS state to zero pulse and the other three LRS states to increasing number of pulses. Therefore, the sensing circuit is able to well tolerate the variations which occur in practical MLC RRAMs. Table III compares the hardware requirements and speed of the proposed sensing scheme (with MOS capacitor) with conventional schemes. Parallel sensing scheme of [19] requires 1M Ω resistors which will be difficult to fabricate in CMOS. In contrast, the circuit of Fig. 3 does not have any passive element and will occupy less area than the sensing circuit of [19]. Further, our sensor scales well from 2-bit to 3-bit MLC by requiring only one additional flip-flop and logic gate (for 3-bit counter). The serial approach will require 7 I REF [20], while the parallel approach will require 7 op-amps and resistors [19] to sense 3-bits/cell.

IV. CONCLUSION
We have proposed a time-based sensing circuit for MLC RRAM which achieves a trade-off between the sequential and parallel sensing mechanisms conventionally used for multilevel memories. The proposed scheme is faster than sequential approach since it senses in a single step and does not require multiple comparisons. The proposed sensing scheme requires less hardware than parallel sensing which uses multiple operational amplifiers in parallel. The time-based sensing circuit tolerates RRAM variations in accordance with the sensed resistance i.e it tolerates more variations at HRS and less and less variations at lower resistances. Such variation tolerance aligns well with RRAM technology whose MLC cells exhibit more variations at HRS. Tolerance to CMOS process variations were studied and found to be reasonable, but the circuit is sensitive to transistor mismatch, which needs to be improved (currentmirror formed by N 1 -N 2 ). The proposed sensing circuit does not require an absolute reference, which conventional Sense-Amplifier based read techniques employ, obviating the need to generate many precise current/voltage references on-chip.