FG Verteilte Systeme und Betriebssysteme
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In dieser Arbeit wird ein umfassendes Betriebssystemkonzept für tief eingebettete Steuersysteme vorgestellt. Das Konzept sieht dabei eine vollständig ereignisbasierte Abarbeitung von Aufgaben vor. Nach einer breiten Domänenanalyse wird gezeigt, welche Vorteile der verfolgte Ansatz hinsichtlich der üblichen Randbedingungen der Zielsysteme hat. Außerdem werden praktische Ergebnisse, welche anhand einer exemplarischen Umsetzung des Konzeptes gewonnen wurde, vorgestellt.
Experiments with wireless sensor networks have shown that unidirectional communication links are quite common. What is even more, they have also shown that the range of a unidirectional link can exceed that of a bidirectional one by far. Still, most of todays routing protocols do not use them, they only eliminate their implications. Those protocols that do use unidirectional links introduce a lot of protocol overhead. One possible conclusion that is often drawn from this fact is that it does not pay to use unidirectional links in a routing protocol. An alternative one is that the overhead produced by the protocols needs to be reduced. This thesis follows the second line of reasoning, and introduces, describes and evaluates five new routing protocols for wireless sensor networks with unidirectional links.
Drahtlose eingebettete Systeme haben vielfältige Anwendungsmöglichkeiten, sei es im Internet der Dinge oder in Sensornetzen. Diese Systeme sollen dabei ohne Eingriff von außen eine hohe Laufzeit erreichen. Die Energieversorgung und der Verbrauch spielen dabei entscheidende Rollen, sind jedoch Varianzen unterworfen. Sollen Wartungsintervalle oder Lebenszeitziele erreicht werden, ist deshalb ein dynamisches Energiemanagement unabdingbar.
In dieser Doktorarbeit wird ein solcher Ansatz vorgestellt, umgesetzt und evaluiert. Im Gegensatz zu existierenden Ansätzen werden Varianzen auf allen drei Ebenen des Managements (Energieversorgung, Energieverbrauch und Energieverwaltung) adressiert. Für die Energieversorgung wird eine Batterieüberwachung vorgestellt, welche eine Steuerung des Verbrauchs ohne komplexe Berechnung des Ladezustands ermöglicht. Der Verbrauch des Systems wird durch einen Software-basierten Ansatz feingranular ermittelt und bezieht Varianzen durch Änderungen der Spannung und der Effizienz von Spannungswandlern ein. Die Verwaltung und Zuordnung der Energie zu Anwendungszielen erfolgt mittels dynamischer Energiebudgets und bietet verschiedene Strategien, um auf Änderungen des Bedarfs adäquat reagieren zu können.
For decades, there has been a distinction between fast, volatile and slow, non-volatile memory technologies in the storage hierarchy of computer systems. While volatile memories offer a byte addressable interface, persistence was limited to slower, block-oriented media. As a consequence, processing and storing information implies copying data from the persistent storage to volatile memory and vice versa.
In recent years, a new memory technology which is both byte-addressable and non-volatile has been announced: Non-Volatile Random Access Memory (NVRAM). Its unique combination of features allows processing of information exactly at the location where it is stored permanently, thereby eliminating the need for copies. Without the need to create and manage copies, data can be processed significantly faster.
The processing of persistent information can be disrupted by failures, like crashes. When changes are only partially performed, data might be left in an inconsistent state. Such a situation can be avoided by creating a copy before starting to change data. That backup is restored when a failure has been detected. Such a procedure relies on a highly specific order of its operations, because the backup can only be disposed after all changes have been carried out successfully. Since NVRAM removes the need for accessing block-oriented media, it removes a major bottleneck in the processing of persistent information, especially when only small amounts of data are modified. As a result, controlling the order of operations dominates the processing performance.
This thesis analyses transactional mechanisms for data on NVRAM which can guarantee that sequences of operations are either carried out as one unit or not at all. The idea is based on creating backups, as sketched above. Existing approaches for the traditional storage hierarchy use separate memory locations for backup and modified data. In a first step, the costs of applying existing procedures to NVRAM are identified. Afterwards, a novel approach which couples the versions tighter in space is presented. Enabled by the unique properties of NVRAM, this new approach is able to reduce the costs of ordering. The processing of persistent data can thereby be sped up significantly.
The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.
Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.
The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.
In the last 30 years, communication became one of the most important pillars of our civilization. Every day terabytes of information are moved wired and wireless between computers. In order to transport this amount of data, researchers and industry increase the data rates of the underlying communication networks with impressive speed. However, such ultra-high data rates are unavailable at the communication endpoints.
One reason why ultra-high data rates are still not available for the communication endpoints is their inability to handle the protocol processing at this data rate. In order to enable communication endpoints to process high-volume data streams, the protocol processing has to be parallelized and optimized on all processing levels. However, parallelization and optimization are cumbersome tasks, which are further complicated as the protocol processing is traditionally carried out by the operating system.
This thesis aims at circumventing these problems by moving the protocol processing into external processing hardware and interpreting communication protocols as stream processing problems. In order to achieve ultra-high data rates at the communication endpoints, a protocol stream processing design approach was developed and evaluated. The design process is separated into implementation, soft real-time analysis, parallelization, and mapping steps, which allow a scalable protocol implementation without paradigm changes. Furthermore, a data link protocol for 100 Gbit/s wireless was developed and implemented with the new stream processing design concept, in order to show its feasibility. The data link protocol is configurable for different communication conditions and easy to parallelize by providing different granularities of packets. The proposed design-process has shown to be suitable for uncovering bottlenecks and helping with debugging the individual stages of the protocol.
System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements.
As the architectural walls drive the number of parallel cores in multicore systems up, it becomes harder to maintain cache coherence across all of the physical memory and all cores. On the other hand, even given a performant cache-coherent system, the unavoidable non-uniform memory (NUMA) and non-uniform cache (NUCA) architectures make programming for it difficult.
A potential solution to this problem is to interpret massive multicore machines as a distributed system with remote memory access, and therefore, use existing distributed programming models. A natural fit for such an approach is the PGAS model, which provides a global address space divided into partitions that can be either local or remote. Unfortunately, completely discarding the notion of sharing ignores the efficient hardware mechanisms available in multicore machines with shared memory.
This survey examines PGAS frameworks and communication libraries with an focus on the PGAS model to enable PGAS applications to exploit shared memory in massive multicore machines without sacrificing the benefits of the PGAS programming model.