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For the third time we were able to hold our PhD workshop "Research is Calling" on smart medical devices and systems, this time in Berlin again. This unique workshop brings together young scientists from computer science and medicine to provide a forum to discuss the very latest approaches to smart medical devices and systems. This year, for the first time, it is possible to publish corresponding workshop proceedings via the publication service of the Brandenburg Technical University (BTU). In our view, this format can create true interdisciplinarity because everyone presents their ideas and interim results to colleagues from a wide variety of disciplines and, conversely, hears and sees the latest from many other specialties. This forum is the vehicle for initiating new collaborations and planning joint research projects. The 'Cottbus project' emerged from personal partnerships between 'technicians' and 'physicians' and was planned from the beginning as a platform and an offer: as a platform for free and fully open scientific exchange and discourse, as an offer to all who are interested, also and gladly beyond Brandenburg. Begun as a "PhD Colloquium", Cottbus' "Research is Calling" is an ideas laboratory for young scientists. Cottbus is to establish a university medical faculty in the next few years as part of the structural change program following the coal phase-out. From our point of view, this lab is an important building block to establish cross-sectional issues right at the interface between medicine and technology, a culture of open discourse and scientific dialogue. The workshop covers the following topics in particular: Smart sensors for medical applications, Low-power wearable sensors, artificial intelligence for medical applications, medical robots, algorithms for medical applications, applications and case studies. Despite the pandemic situation the workshop could be held in presence. In five exciting presentations new ideas and cooperation possibilities were shown. Two keynotes (including Alina Nechyporenko, Marcus Frohme as special guests) and a dinner rounded off the program. At this point we would like to thank all participants, the reviewers, and the organizers, Stefan Scharoba and Kathleen Galke. We look forward to establishing this event as permanent and reaching an ever-growing audience.
Sowohl in Anlagen mit Hochgeschwindigkeitsrechensystemen als auch in der Industrie in so genannten smarten Problemlösungen spielen Rechenbeschleuniger eine immer bedeutendere Rolle. Diese wissenschaftliche Arbeit befasst mich mit der Untersuchung anwendungsorientierter FPGA-Architekturen, um die Lücke zwischen Performanz und Energieverbrauch zu verkleinern oder gar zu schließen. Sie untersucht zunächst die optimale Granularität einer Architektur für einen Algorithmus. Anhand der Auswertung einer umfangreichen Versuchsreihe mit ca. 650 Simulationen und etwa 200 verschiedenen Architekturen wird versucht einen FPGA mit optimalen Eigenschaften für eine Beschleunigerhardware abzuleiten. Für die Untersuchung wird das Evaluationswerkzeugs Verilog-To-Routing genutzt, dessen Steuerung nebst dem Parsen der Ergebnisse mittels Python automatisiert wird. Basierend auf den Ergebnissen dieser Granularitätsuntersuchung wird die Einführung einer parameterisierbaren CGRA-Architektur beschrieben, welche als Overlay auf einer beliebigen FPGA-Architektur aufgebracht werden kann. Die ersten Ergebnisse einer Evaluation mit einem Faltungsalgorithmus weisen auf Probleme beim Datentransfer zwischen einem Prozessorsystem und dem VCGRA als Beschleuniger hin, weshalb in zusätzliche Module für eine Entspannung dieses Flaschenhalses investiert wird. Aus Überlegungen entstehen so genannte Pre-Fetcher und Datenpuffer, eine Memory Management Unit und eine zentrale Steuerstelle, die Central Control Unit, welche das VCGRA zu einer Gesamtarchitektur ergänzen. Die Entwicklungsschritte und Evaluation dieser zusätzlichen Module erfolgt nun in SystemC, statt in VHDL, um den Zyklus von Design und Evaluation zu verkürzen. Im Zusammenhang mit der Central Control Unit wird ein Maschinencode im Binärformat und ein passender Assemblerbefehlssatz entworfen, um das VCGRA autark zu steuern. Alle Werkzeuge und die Architektur stehen unter Open-Source- Lizenzen der wissenschaftlichen Community zur Verfügung.
This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.