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1. Memristor-Symposium 2023
(2023)
The 1.Memristor-Symposium was held from 27-28.02.2023 in Bamberg. Young scientists and PhD students presented their research and covered several topics regarding ongoing memristive research in Germany. Several talks on the topic of memristive devices, their testing, modeling and usage were presented and discussed, covering the whole vertical integration from material and divice up to application level.
For the third time we were able to hold our PhD workshop "Research is Calling" on smart medical devices and systems, this time in Berlin again. This unique workshop brings together young scientists from computer science and medicine to provide a forum to discuss the very latest approaches to smart medical devices and systems. This year, for the first time, it is possible to publish corresponding workshop proceedings via the publication service of the Brandenburg Technical University (BTU). In our view, this format can create true interdisciplinarity because everyone presents their ideas and interim results to colleagues from a wide variety of disciplines and, conversely, hears and sees the latest from many other specialties. This forum is the vehicle for initiating new collaborations and planning joint research projects. The 'Cottbus project' emerged from personal partnerships between 'technicians' and 'physicians' and was planned from the beginning as a platform and an offer: as a platform for free and fully open scientific exchange and discourse, as an offer to all who are interested, also and gladly beyond Brandenburg. Begun as a "PhD Colloquium", Cottbus' "Research is Calling" is an ideas laboratory for young scientists. Cottbus is to establish a university medical faculty in the next few years as part of the structural change program following the coal phase-out. From our point of view, this lab is an important building block to establish cross-sectional issues right at the interface between medicine and technology, a culture of open discourse and scientific dialogue. The workshop covers the following topics in particular: Smart sensors for medical applications, Low-power wearable sensors, artificial intelligence for medical applications, medical robots, algorithms for medical applications, applications and case studies. Despite the pandemic situation the workshop could be held in presence. In five exciting presentations new ideas and cooperation possibilities were shown. Two keynotes (including Alina Nechyporenko, Marcus Frohme as special guests) and a dinner rounded off the program. At this point we would like to thank all participants, the reviewers, and the organizers, Stefan Scharoba and Kathleen Galke. We look forward to establishing this event as permanent and reaching an ever-growing audience.
This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.
This thesis introduces a comprehensive approach for making a particular class of embedded processors self-testing and self-repairing, such that a limited amount of permanent hardware faults that occur during the lifetime of these processors in the field will not prohibit the functional behavior of the user application running on the processor. The presented concepts all use redundant hardware, but the techniques used for administrating the hardware-redundancy range from hardware-based methods over hybrid methods to pure software-based methods, whereby the focus is on the latter ones. The proposed methods will be demonstrated by using a processor that is well designed for diagnostic self-test and self-repair purposes. This will also highlight some architectural properties of such a processor, which are beneficial for performing a software-based self-test and self-repair process.
Chapter 1 is an introduction to the field of dependable systems and fault tolerance. Fundamental terms and notations, which are used throughout this thesis for classification and evaluation, are provided. The used processor model – the VARP processor – is introduced in chapter 2 together with a hardware-based self-repair scheme for that processor. The results are used as reference values for evaluating the software-based methods. Chapter 3 introduces the fundamental concept of the software-based self-repair. In chapter 4 hybrid methods are derived by combining software-based and hardware-based methods, highlighting the synergy effects of the combination. Finally, in chapter 5, a diagnostic and adaptive software-based self-test scheme is introduced. This self-test scheme provides the diagnostic capability that is needed in the field for identifying defect components in the VARP processor and completes the comprehensive software-based self-test and self-repair approach.
The reliability of interconnects on integrated circuits (IC) has become a major problem in recent years because of the rise of complexity, the low-k-insulating material with reduced stability, and wear-out-effects from high current densities. The total reliability of a system on a chip is increasingly influenced by the reliability of the interconnections, which is caused by increased communication from the elevated number of integrated functional units. In recent years, studies have predicted that static faults will occur more often decreasing the reliability and the mean time to failure. The most published solutions aim to prevent dynamic faults and to correct transient faults. However, built-in self-repair (BISR) as a solution for static faults has not previously been discussed along with the other possible solutions. Theoretically, BISR can lead to higher reliability and lifetime. This is my motivation to implement BISR for integrated interconnects. Because BISR cannot repair transient and dynamic faults, I combine BISR with other approved solutions in this thesis. The results show that the combination leads to higher reliability and lifetime with less area and static power overhead compared to the existing solutions.