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- FG Systeme (22)
Conventional semiconductor memories are facing many challenges concerning their yield, reliability, testability, and manufacturability as the feature size decreases. Although they are used in the vast majority of electronic devices, their applicability for upcoming digital systems is questionable. On the other hand, due to unprecedented development of mobile devices even faster, denser, and more power-efficient semiconductor memories are required. As a consequence, many researchers and system designers are seeking new memory solutions. The greatest attention is paid to solid-state, non-volatile memories (NVMs) such as PCRAMs, MRAMs/STT-MRAMs, FeRAMs, and RRAMs. Due to their promising features like non-volatility, low-power consumption, and great scalability they are expected to meet the challenging demands of future digital systems.
Unfortunately, despite all advantages they offer, emerging NVMs pose some peculiar characteristics like limited endurance, variable data retention time, or vulnerability to external factors. On top of that, they are still in early-maturity state where their fabrication processes are not of high quality and are prone to high variations. Because of that, emerging NVMs may suffer from permanent faults which can occur right after production or in the field, during their operational time. As a consequence, the reliability of new memory technologies requires special management and great improvement.
The thesis introduces system-level approach aimed at comprehensive reliability management of existing and emerging NVMs. It presents novel on-line repair techniques which focus on specific issues of NVMs. The block-level repair manages post-production faults in the memory array. The word-level repair aims at hard faults caused by wear-out memory cells. Finally, the error-correcting code with increased hard-error correction capability handles soft and hard errors in the memory array.
Because proposed techniques are based on similar principles, they can be combined into a consistent system. Depending on the way how they are connected, different repair schemes can be achieved. Moreover, by merging them into the system a synergistic effect can be produced where the achieved memory reliability improvement is greater than the sum of reliability improvements achieved with their standalone implementations.
Further in the thesis, such a consistent repair system is presented. Next, its effectiveness, repair capabilities, and applicability for an embedded system are evaluated. In addition, the achieved synergistic effect is described and quantified
Hardwareimplementierte latenzarme drahtlose Medienzugriffsprotokolle für höchsten Datendurchsatz
(2014)
Der Fortschritt der Technik ermöglicht immer leistungsfähigere drahtlose Dienste mit hohen Anforderungen an Latenz, Jitter und Übertragungsgeschwindigkeit. Aktuelle digitale Protokolle für drahtgebundene hochauflösende Multimediaübertragungen (HDMI, DisplayPort) oder Peripherieschnittstellen (USB, PCIe, SATA) in der Computertechnik erreichen Datenraten im Multi-Gigabit Bereich. Die Übertragung der Inhalte z.B. Filme, Musikstreaming oder Dateiübertragungen mit Hilfe breitbandiger drahtloser Übertragungsverfahren vereinfacht die kabellose „Installation“ und die daraus folgende Benutzerfreundlichkeit (Mobilität) im Heimbereich (Indoor). Weiterhin werden Systeme mit hohen Datenraten und kleinen Latenzen unter 5 ms im Mobilfunkbereich benötigt, um Basisstationen (3G, LTE) mit dem Kernnetzwerk zu verbinden. Diese Backhaul-Verbindungen können auch im innerstädtischen Bereich zum Aufbau von Small-Cell-Installationen genutzt werden, da nicht immer eine Kabelverlegung möglich ist. Eine Verkettung der Verbindungen vergrößert den Abstand zum Zugangspunkt des Kernnetzes und stellt zusätzliche Anschlußpunkte für Basisstationen bereit. Allerdings vergrößert sich auch die Latenz für die weiter entfernten Stationen.
In dieser Arbeit wird ein MAC-Protokoll für hochratige und latenzarme drahtlose Verbindungen vorgestellt. Dazu werden sowohl Punkt-zu-Punkt- als auch Punkt-zu-Mehrpunkt-Verbindungen auf ihre speziellen Anforderungen bei der Implementierung der MAC-Komponenten in einer programmierbaren Hardware (FPGA) analysiert. Eine Integration des MAC-Protokolls zusammen mit einem OFDM-Basisbandprozessor mit Brutto-Datenraten größer 5 GBit/s erlaubt die Überprüfung der Funktionalität sowie die Messung wichtiger Protokollparameter unter realen Einsatzbedingungen. Das vorgeschlagene Medienzugriffsprotokoll unterstützt den Einsatz von Beamsteering-Verfahren zur Suche von benachbarten Kommunikationsteilnehmern und den gleichzeitigen räumlich getrennten Kanalzugriff mehrerer Kommunikationsteilnehmer. Eine Anwendungsschnittstelle für nutzerspezifische Implementierungen mit exklusivem Zugriff auf das Übertragungsmedium erleichtert die Integration zusätzlicher Funktionalität wie z.B. eine hochauflösende Entfernungsmessung. Weiterhin wird ein Verfahren zur latenzarmen Detektierung und Umschaltung blockierter Pfade vorgestellt. Umfangreiche Simulationen bestätigen die Funktionalität des MAC-Protokolls in unterschiedlichen Szenarien mit und ohne Übertragungsfehler.
The design of embedded sensor node hardware systems is a challenging task driven by the increasing demands for low power, high efficiency, low cost and small size. These unique requirements make the usage of off-the-shelf general purpose microcontrollers fairly inefficient. For many wireless sensor network applications, the design of a dedicated low power sensor node microcontroller is the only way to answer specific application requirements. According to the trends in device, process and design technology, the development of sensor node devices is relying on a cheap planar bulk-CMOS technology, where power consumption is dominated by static power loss caused by high leakage currents. To keep the power at acceptable level, designers are compelled to apply the methodologies based on advanced low power techniques that target both static and dynamic power in the chip. The decisions made early in design phase are likely to determine the energy efficiency of the final design. Therefore, the choice of power saving strategy is the key challenge in designing energy-efficient sensor node hardware.
This work presents a methodology that assists designers meeting the critical design decisions regarding power, early in the design process. The presented methodology extracts the activity profiles of single system components and applies them in the developed models for energy estimation of particular low power implementation. The energy estimation models account for the energy overhead introduced by specific low power techniques, enabling comprehensive exploration of system’s energy efficiency in a given application scenario. Special attention is paid to the methodology utilization in typical wireless sensor network applications. Accordingly, the examples of activity profiling in wireless sensor node systems are presented. The proposed methodology is integrated within a power-driven design flow and applied to the design of an embedded sensor node microcontroller. This methodology is used to perform the cross comparison of alternative low power implementations for the target system architecture. The implementation relying on concurrent clock and power gating is selected as the most energy efficient and consequently realised. Power switching cells and power control logic have been designed and characterized. Also, the final system architecture, basic system components and applied design process are described. Finally, the developed power-gated sensor node microcontroller is implemented, fabricated and successfully tested. The chip measurements results are presented and analyzed.
The analysis of different low power approaches applied to the target system architecture has shown large impact of clock gating on the system energy. In a given application scenario, the clock gating implementation has reduced 72 times the dynamic energy and 12 times the total energy of the system. The implementation of power gating technique has gained 2.8 times reduction of the leakage energy and 2 times reduction of the total system energy compared to the clock gating only implementation. The analysis of two alternative power gating approaches has emphasized the significance of partitioning in power-gated design. A heuristic partitioning that combines two specific blocks having successive activity phases into a single power domain, thereby reducing design complexity and chip area, has been shown to have positive impact on the energy efficiency of the target design.
Despite the numerous benefits that Integrated Circuit (IC) technology downscaling brings, it also introduces many challenges. First of all, IC dependability is lowering: both lifetime reliability and resilience to single event effects is decreasing. Another major problem is the increased power consumption. On the other hand, the vast available space enables integrating hundreds of processor cores in a single chip! Multiprocessing is for over a decade the main architectural trend because of two reasons. Firstly, the performance of single processors gained by architectural innovations reached the upper limit i.e., the point of diminishing returns. Secondly, the operating frequency could not be increased due to the excessive power consumption, as pointed out. This work proposes a multiprocessor architectural framework that addresses many challenges related to dependability, power consumption and performance. The key idea is dynamical adaptation to the application requirements of fault tolerance and performance, which is possibly done at the lowest rates of aging and power dissipation. The application may select one of the three basic operating modes: de-stress, fault-tolerant and high-performance. De-stress mode prolongs multiprocessor lifetime and reduces power consumption by using core gating patterns that systematically power- or clock-off entire cores in the multiprocessor. These patterns use the information supplied by novel IC aging monitors. Fault-tolerant mode, on the other hand, increases error resilience by forming core-level NMR (N-modular redundant) systems using the multiprocessor cores. That is, entire cores are tightly synchronized to execute the same task simultaneously. Voting is done on each clock cycle using special, programmable NMR voters. Core-level NMR enables masking faults without invoking recovery procedures which is appreciated by timing-critical, or, real-time applications. Finally, high-performance mode is used for boosting multiprocessor performance. The framework is evaluated using a novel environment for automated fault injection, as well as a novel multiprocessor verification platform. A vast number of experiments were made which led to closed-form expressions that determine the number of cores N required to survive the projected mission time, given the fault rate. Moreover, a newly-developed method for lifetime evaluation based on the Weibul distribution shows the benefits of using core gating patterns. E.g., the new Youngest-First Round-Robin (YFRR) pattern enables up to 31% increase in system's lifetime compared to a simple Round-Robin.
During the last years, the asynchronous design style has been rediscovered as a potential solution to upcoming design issues in deep-submicron technologies. However, besides the lack of commercial tools supporting this design style, one major challenge is the test of asynchronous designs. Especially their event-driven behavior leads to problems during test. Basically, the timing of asynchronous circuits is determined by gate and wire delays that are sensitive to variations of environmental parameters (process, voltage and temperature). This leads to uncertainties in the timing of the responses. Consequently, standard commercial test systems cannot be used, because such systems read the responses at specific cycles and, therefore, could reject fault-free devices. Furthermore, available hardware testers are, in principle, not designed to react to signal events from the design-under-test as it is necessary to establish asynchronous communication via handshake signalling. As a result, even simple functional tests that only apply stimuli and read the responses of the design-under-test cannot be realized without preparatory measures. This work addresses these issues and proposes a concept to enable functional tests of asynchronous designs. The concept is based on a special test processor that provides generic interfaces used to establish asynchronous handshake communication with a device-under-test. By this, elastic functional tests can be realized that overcome the static timing of conventional tests and emulate the real operating environment of the design. Apart from the generic test processor architecture, an essential part of the concept deals with the establishment of the processor as a stand alone or embedded test equipment. A workflow is provided that describes how the device-under-test can be embedded into the test processor environment for performing the tests. Besides the interconnection between the asynchronous design and the test processor, this especially includes the generation of programs that realize the functional tests of the design. A methodology is introduced that generates the desired programs for the processor from a standard functional simulation of the design-under-test. Based on the generic concept, a framework including both a test processor implementation and the realization of the program generation is delivered. In order to evaluate the entire concept, this framework has been applied to functionally test an asynchronous arithmetic-logic-unit. In combination with additional experiments, conducted to determine the required resources, it has been shown that the introduced concept is a suitable approach to test asynchronous designs.
The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.
In dieser Arbeit wird ein neues Konzept für den Entwurf fehlertoleranter digitaler Schaltungen vorgestellt. Die als spezifische Fehlertoleranz bezeichnete Entwurfsmethode erweitert den Stand der Technik um die Möglichkeit, Fehlertoleranz gezielt für gewünschte Ein- und Ausgabezuweisungen einer Schaltung bereitzustellen. Die generell sehr aufwändigen Maßnahmen zur Realisierung von Fehlertoleranz lassen sich so an die tatsächlich vorhandenen Zuverlässigkeitsanforderungen einer gegebenen Anwendung anpassen, was im Vergleich zu herkömmlichen Verfahren zu erheblichen Kosteneinsparungen im Hinblick auf Hardware und Stromverbrauch führt. Die Eingaben einer Schaltung werden dazu mit ihren zugehörigen Ausgaben in kritische und unkritische Signale unterteilt. Für kritische Signale wird das gleiche Maß an Fehlertoleranz bereitgestellt, wie es auch durch das Verfahren der dreifach modularen Redundanz garantiert wird. Unkritische Signale werden nicht fehlertolerant ausgelegt, da das für solche Signale nicht gefordert werden muss. Im Bezug auf kombinatorische Schaltungen wird dieses Grundprinzip auf eine beliebig wählbare Teilmenge aller möglichen Eingaben mit ihren zugehörigen Ausgaben angewendet. Die nicht zu schützenden, unkritischen Signale werden zu Optimierungszwecken genutzt. Genau diese Freiheit im Entwurfsprozess ermöglicht beim Entwurf fehlertoleranter Schaltungen signifikante Kosteneinsparungen, die bislang durch andere Verfahren nicht berücksichtigt wurden. Bei sequentiellen Schaltungen wird das Konzept auf Eingabefolgen und ihre entsprechend zugehörigen Ausgabefolgen abgebildet. Ab einem bestimmten Zustand werden in Schaltungen, die nach diesem Prinzip entworfen wurden, alle als kritisch eingestuften Eingabefolgen fehlertolerant verarbeitet, woraufhin die sequentielle Schaltung entsprechend fehlertolerante Ausgabefolgen liefert. Die Länge der kritischen Eingabefolgen und die Anzahl der Zustände, von denen aus eine fehlertolerante Verarbeitung der Eingaben gefordert wird, ist beliebig wählbar. Neben der Beschreibung des Grundkonzeptes der spezifischen Fehlertoleranz für kombinatorische und sequentielle Schaltungen beinhaltet die Arbeit Erweiterungen, mit denen sich die durch das Verfahren bereitgestellte Fehlertoleranz erhöhen lässt. Es wird zudem erläutert, wie die spezifische Fehlertoleranz ohne besonderen Aufwand mit Hilfe gängiger Werkzeuge im Schaltungsentwurf umgesetzt werden kann. Vom Entwerfer werden dazu keine speziellen Kenntnisse über das eigentliche Verfahren vorausgesetzt. Anhand experimenteller Ergebnisse wird auch gezeigt, welche Einsparungen sich durch die spezifische Fehlertoleranz im Vergleich zu herkömmlichen Verfahren aus diesem Bereich ergeben. Dazu wurden verschiedene Benchmark-Schaltungen mit der spezifischen Fehlertoleranz implementiert und ihre Gesamtflächen den Flächen entsprechender Schaltungen, die nach dem Prinzip der dreifach modularen Redundanz entworfen wurden, gegenübergestellt.
Latenzverringerung in Basisbandprozessoren am Beispiel eines hochratigen OFDM-Kommunikationssystems
(2012)
In modernen digitalen Übertragungssystemen ist der gesamte Datendurchsatz nicht mehr allein durch die Datenrate – z. B. aufgrund der begrenzten Bandbreite – eingeschränkt. Stattdessen haben die bei der Verarbeitung entstehenden Latenzen einen immer größeren Einfluss auf die erzielbare Systemperformance. In der Fachliteratur beschriebene Untersuchungen zur Latenzverringerung in digitalen Basisbandprozessoren beschränken sich meist auf die Optimierung eigenständiger Module. Im Rahmen dieser Arbeit werden, basierend auf einer Untersuchung der Basisbandmodule auf ihren Latenzbeitrag und einer Darstellung der Latenzauswirkungen, bestehende Verfahren der Latenzverringerung evaluiert und neue Verfahren zur Latenzreduktion entworfen. Die praktischen Auswirkungen werden dabei anhand der Latenzmodellierung eines bestehenden 60 GHz-OFDM-Kommunikationssystems aufgezeigt. Die zur Anwendung der neu entworfenen Verfahren notwendigen strukturellen Änderungen in der Basisbandverarbeitung werden detailliert dargestellt. Weiterhin wird eine allgemeine Methodik des latenzarmen Systementwurfs vorgestellt, die die Anwendung der neu entworfenen Verfahren beinhaltet. Bei der Darstellung von Verfahren zur Latenzverringerung liegt der Schwerpunkt auf der zur Durchsatzsteigerung üblicherweise verwendeten, aber noch nicht im Zusammenhang mit der Latenzverringerung beschriebenen Anwendung von parallelen Datenverarbeitungsstrukturen sowie auf der neu vorgeschlagenen Anwendung von Spekulation. Mithilfe der spekulativen Demodulation und der spekulativen Dekodierung lassen sich Latenzen aufgrund von Abhängigkeiten in der Datenverarbeitung einfach vermeiden. Die sich aus den spekulativen Verfahren ergebenden Auswirkungen auf die MAC-Ebene werden zum Schluss kurz diskutiert.
Ziel dieser Dissertation war es, die Eignung von Ultra-Breitband-Pulsfunk (IR-UWB) für die drahtlose Kommunikation in der Sensor/Aktor-Ebene der Fertigungsautomatisierung zu untersuchen. Dazu wurde ein drahtloses Kommunikationssystem auf Basis standardisierter Protokolle entworfen und untersucht. Diese Anwendung erfordert die Erfüllung harter Echtzeitfähigkeit im Bereich weniger Millisekunden in industriellen Umgebungen. Ein solches Umfeld stellt aufgrund eines hohen Rauschpegels und vieler metallischer Oberflächen, die Multipfad-Effekte verursachen, sehr hohe Ansprüche an das Latenzverhalten und die Robustheit. Deshalb waren die Hauptziele die Reduzierung von Latenz und gleichzeitige Erhöhung der Robustheit für den existierenden, auf IR-UWB basierenden Standard IEEE 802.15.4a. Dieser Standard ist unter anderem deshalb vielversprechend, da er sich mit sehr preisgünstigen, nicht-kohärenten Empfängern von geringer Komplexität umsetzen lässt, die trotzdem relativ robust gegenüber Multipfad-Effekten sind. Es wurde gezeigt, dass sich auch mit diesen günstigen Geräten durch Optimierung des Standards eine hohe übertragungssicherheit bei geringer Latenz realisieren lässt. Es wurden Modifikationen zur Optimierung der Robustheit und Latenz des bisher üblichen Designs von nicht-kohärenten IR-UWB-Empfängern vorgestellt. Durch Ergänzungen zu der im Standard beschriebenen Modulation und Kodierung konnte die Verlässlichkeit zusätzlich gesteigert werden. Um diese optimierte PHY-Schicht effizient einsetzen zu können, wurde eine spezialisierte MAC-Schicht für die Automatisierung, die in einem Entwurf für den kommenden Standard IEEE 802.15.4e beschrieben wird, eingesetzt. Da bei dieser MAC-Schicht die Kommunikationsmuster im Voraus bekannt sind, war weitere schichtübergreifende, applikations-spezifische Optimierung möglich, die eine weitere Reduzierung der Latenz sowie eine Erhöhung der Robustheit erbrachte. Im Zuge der Arbeit wurde ein flexibel konfigurierbarer Simulator für IR-UWB auf Basis von industriell akzeptierten Kanalmodellen erstellt. Dieser Simulator wurde auch zur Evaluation und Verifikation der Forschungsergebnisse benutzt. Das entworfene Gesamtsystem ist über mehrere Parameter konfigurierbar und dadurch an weitere Anwendungen in der Automatisierung anpassbar. Eine dieser Konfigurationen wurde durch Simulation evaluiert. Sie zeigt mindestens die gleiche und zum Teil bessere Performance als bisherige drahtlose oder drahtgebundene Lösungen für die Sensor/Aktor-Ebene der Fertigungsautomatisierung, wie z.B. AS-Interface, Bluetooth I/O oder WISA. Für den repräsentativen Fall von 32 Teilnehmern mit jeweils einem Byte Prozessdaten erreicht sie eine Zykluszeit von 1,88 ms. Damit kann eine eine mittlere Reaktionszeit von 985 µs erreicht werden und eine harte Echtzeitschranke von 15 ms mit einer Fehlerwahrscheinlichkeit unter 10^-9 eingehalten werden. Das Kommunikationssystem wurde auch in Hardware auf FPGA-Basis implementiert. Da das benutzte analoge Front-End, ein früher Prototyp eines IEEE 802.15.4a-kompatiblen Front-Ends, noch keine repräsentativen Messungen zuließ, wurde die Funktion durch eine Basisbandverbindung über Kabel verifiziert.
High-speed data capturing components for Super Resolution Maximum Length Binary Sequence UWB Radar
(2011)
Within framework of UKoLoS project the new Super Resolution Maximum Length Binary Sequence UWB Radar (M-sequence radar) was developed. The radar consists of an M-sequence generator, transmitter front-end, receiver front-end, data capturing device and data processing blocks, whose design responsibilities were carried out by four institutions. In this thesis the design and measurements of the data capturing device components is described. Logically the data capturing device can be divided into three parts; a capturing part, realized with the high-speed analog-to-digital converter, a predictor, realized with the high-speed digital-to-analog converter and a subtraction amplifier, which in this particular work is integrated into the receiver front-end. The main challenge of the work is to implement the A/D converter, which works at full speed of the radar. Despite the radar architecture allows capturing data with undersampling, it leads to waste of transmitted energy. Therefore the ADC has to capture reflected signal with the full system clock rate of 10 GHz and should have a full Nyquist 5 GHz effective resolution bandwidth. Implementation of the conventional 4-bit full flash ADC with specified bandwidth is not possible in the IHP SiGe BiCMOS technology because some critical blocks, namely the reference network, can not achieve 5 GHz effective resolution bandwidth. To overcome this problem a new configuration of the differential reference network is proposed. The new reference network has a segmented, free configurable architecture. As extreme case it can be realized as a full parallel network and in such configuration the maximal bandwidth can be achieved. The proposed network was implemented in the A/D converter and measured. The bandwidth of the ADC with new network is several times higher than the bandwidth of the conventional ADC,while keeping power dissipation the same. Further the proposed network has possibility to equalize the bandwidth in each output node and in that way optimize overall power dissipation. The other advantage is the possibility of electronic calibration of separate voltage shift in the network. The second component of the data capturing device is the D/A converter, which is required to have the accuracy which corresponds to full accuracy of the data capturing device, better than 0.2% in our case. Measurements showed that error due to mismatch of the components was 10 times higher than required. To meet the accuracy specification an external off-line calibration of the DAC was implemented. Using calibration the predictor errors less than 0.15% were achieved.
The development of secure systems is already a very challenging task. In the domain of wireless sensor networks this challenge is even aggravated by severe constraints of the sensor node devices and the exposed character of the networks. To cope with this issue, this thesis proposes a tool-supported development flow named configKIT, that helps users to integrate secured applications in the domain of Wireless Sensor Networks. It is a component-based framework that selects and composes configurations of hardware and software components for WSN applications from high-level user requirements, automatically. Therefore, the composition process utilizes a flexible meta-model to describe properties of the components, the requirements, and the system semantics, which allows the assessment of the behavior of the composed system. Based on this modeling technology five practical security models are investigated, which base on different technical views on a general security ontology for WSNs. Each model is discussed theoretically and practically, based on a practical integration in the configKIT framework. The configuration toolkit and the security models are finally evaluated by applying the techniques developed to the non-trivial example of secure in-network aggregation. The evaluation shows that all five practical security models developed in this thesis work correctly and with reasonable model overhead. These results promote the notion of a practically applicable toolkit to configure secure applications in WSNs.
Wireless sensor networks (WSNs) are built of cheap, resource constraint devices, capable to collect process and communicate data. WSN applications depend on the data they collect. In other words, the applications require the data to be available, even if some WSN nodes fail. The challenge is that nodes are prone to fail and todays WSNs do not provide highly reliable data storage. Thus, the quality of the service provided by the system, regarding the data handling, is one of the most important factors. Data replication increases the availability of the data and thus, the robustness and quality of the data storage. But the existence of several copies of data items in the WSN induces the data consistency to become of high importance in order to ensure proper behavior of the application. This work investigates the feasibility of data consistency models used in distributed shared memory in WSNs to provide more powerful distributed systems with reliable data exchange. As a starting point WSNs and consistency approaches are introduced. Based on those basics, the mechanisms needed to allow for data consistency are discussed as a theoretical framework for the prototypical implementation of a data consistency providing middleware, which was implemented as part of this work. The middleware adapts the mechanisms known from original memory consistency approaches to be usable in the sensor network area and proposes own, low cost mechanisms, as well. The latter are at least partially based on the idea that within the shared memory of WSNs information is the major concern and that by that the replica update rates can be tailored to the application. In order to allow for ease of use of the middleware the replication schemes and consistency mechanisms can be defined by the application engineer as a policy. The latter is transformed and injected into the middleware code by a pre-compiler, so that the application engineer no longer needs to implement replication and consistency mechanisms herself. The most appropriate memory consistency models are implemented and evaluated using the framework proposed in this thesis.
The license-free 60 GHz band enables a new breed of wireless networks offering data rates in the range of one to a few Gigabit per second over short distances. This thesis investigates the performance of a 60 GHz system using coded OFDM modulation and directive antennas for the transmitter and receiver. The study includes the impact of the 60 GHz propagation channel, impairments of a frontend in Si-Ge technology and considerations with respect to an efficient implementation. A major part of the work consists in the specification of a physical layer, which is optimized for the given wireless link and enables an implementation with programmable logic devices at moderate clock speed. For the selection of a channel code, the performance of two coding schemes is compared for the 60 GHz channel. The first scheme consists of a standard convolutional code and an outer Reed-Solomon code, whereas the second scheme is made up of an LDPC code with similar complexity. The interleaving scheme for the convolutional code is optimized to yield best performance. Furthermore, algorithms are developed and simulated for all essential system components of the OFDM receiver. The implementation of these components is also considered. A new synchronization scheme is introduced, which offers a high degree of robustness at low complexity. In this scheme, the fine timing synchronization shares the same hardware resources as the channel estimator. This approach results in a significant reduction of chip area. A new tracking algorithm is developed, which adequately compensates for the fluctuations of carrier phase, timing and channel impulse response. Finally, the implementation of the FFT and Viterbi decoder is discussed. The system architecture of the receiver requires a high degree of parallel processing and uses a deep processing pipeline to keep the clock frequency low. It is shown how to combine the system components into an efficient system under these conditions. The performance of the complete system is investigated for the static and time-variant channel. It is shown that despite the low complexity and high latency, the system achieves good performance. The baseband processor has been realized as a narrowband version with 400 MHz channels and broadband version with 2 GHz channels and improved algorithms. This has been done on an FPGA platform.
The goal of this thesis is the analysis of the challenges and finding solutions for the design of mm-wave transceivers. The work presented here is focused on design of transmitter (TX) components, which are critical for the performance of the whole analog front-end. Phase-locked loop (PLL) phase noise is optimized, an image-rejection filter and a high 1 dB compression point (P1dB) power amplifier (PA) are designed. The PLL phase noise optimization is presented and different PLL topologies are compared. A new optimized recipe for calculating PLL parameters of a forth order PLL is presented. Using this approach the spurious sidebands can be reduced by up to 10 dB. The image-rejection filter chapter analyzes the challenges related to the design of the integrated image–rejection filter. The analysis presented here is the first on integrated filters for the 60 GHz band, because the previously published work dealt with on-board filters. The main problems related to the design of integrated filters arise from the low quality factor of the integrated resonators. The effects are high insertion loss and low selectivity. Two measures to reduce the insertion loss of the image–rejection filters were suggested. One is to design the filter as broadband. This measure deteriorates selectivity, so the minimum required image–rejection will limit the width of the passband. The second measure is to design the filter as broadband with non-equidistant transmission zeros (i.e. asynchronously tuned filter). This measure will improve both the insertion loss and the image–rejection. The challenges related to the design of mm-wave PAs with high P1dB are analyzed and the procedure of the PA design is presented. The difficulties related to the PA design and layout are discussed and optimum solutions presented. Limits of different power combining techniques for integrated PAs are discussed. Effects of poor on-chip ground connection are analyzed. Different causes for P1dB degradation are analyzed. The produced PA features a differential cascode topology. The layout is symmetrical and presents a virtual ground on the symmetry line for the differential signal. The optimized schematic and a symmetrically drawn layout resulted in a 17 dBm measured P1dB. It was the highest reported P1dB in 60 GHz SiGe PAs when it was published. The fully integrated TX was used for data transmission with data rate of 3.6 Gbit/s (with coding 4.8 Gbit/s) over 15 meters. This is the best result in the class of 60 GHz AFEs without beamforming.
Definition and configuration of reliable event detection for application in wireless sensor networks
(2010)
Ubiquitous systems based on wireless sensor networks will amazingly increase our quality of life. These systems are to be deployed in large areas with high density where hundreds or thousands of nodes are used. Certainly that demands to use low cost devices with limited resources, which in turn are prone to faulty behaviour. This work introduces a novel concept for wireless sensor network configuration considering fault tolerance, energy efficiency and convenience as primary goals while being tailored to user needs. It allows to ignore low-level details like node resources, network structures, node availability etc. and enables the programmer to work on a high abstraction level, namely the event itself including event related constraints. The definition of events characterising real world phenomena is of prominent use in sensor networks. The presented concept autonomously configures and monitors events, even if it requires to organise collaboration between nodes to deliver the results. The contribution of this work is threefold. An intuitive XML-based ESL simplifies event configuration to a level that is even suitable for non-professionals. It features hardware independent description elements to define complex phenomena and enhances these by tailor-made voting schemes and application constraints. Based on that, a novel, fully decentralised mechanism to autonomously set up distributed event detection called EDT and a cost efficient means to maintain such EDT, are presented. EDTs can be efficiently constructed on every device by using a tiny generating finite state machine requiring eight states only. It enables every node to self-divide event queries according to its own resources and self-adapt to the tasks assigned. Simultaneously, the EDT provides the interface for efficient collaboration using a lease-based publish/subscribe approach. The simulations clearly show that this concept works well and the applied collaboration scheme outperforms even idealised acknowledgement-based approaches. On top of the EDT, a means is developed that enhances the reliability of detection beyond the scope of Boolean event decision. It examines behavioural trends in sensor readings to indicate the significance of actual measurements in relation to the configured event. Measured data is investigated in detail to finally attach a significance indicator "is" to each event. This automatically generated indicator shall support users or overlaying systems in decision-making. In the example scenario based on data of real test cases, the "is" indicates a flaming fire 88 seconds and a smouldering fire 48 seconds before the threshold-based method triggers the alarm.
Privacy issues are becoming more and more important, especially since the cyber and the real world are converging up to certain extent when using mobile devices. Means that really protect privacy are still missing. The problem is, as soon as a user provides data to a service provider the user looses control over her/his data. The simple solution is not to provide any data but then many useful services, e.g., navigation applications, cannot be used. The dissertation addresses two aspects of privacy protection. The first aspect regards not producing private information if possible. Such unnecessary information are traces of access controlled service uses. Hence, one approach in this dissertation enables k-anonymous authorization for services uses. It equips the users of the system with trusted pseudonymous certificates reflecting their respective authorizations. Analogous to anonymous e-cash, the certificates are issued by a trusted authority with knowledge of the actual authorizations of an identified user. The certificates can be verified by any service supported by the trusted authority but without knowledge of the user’s identity. Not even the issuing authority is able to reveal the users identity from the pseudonym of a certificate. Hence, service usage cannot be tracked, neither by the service nor by the authority. This protects the privacy of service usage behavior of users. The second aspect of privacy protection is to remain in control over private data released to others. Temporary release of private data is essential to context-sensitive services, which rely on these context data to provide or improve added value. Therefore, the dissertation designs a Privacy Guaranteeing Execution Container (PGEC), which enables applications to access private user data and guarantees that the user data is deleted as soon as the service or application is finished. Basically, the concept is that the application obtains access to the user data in a specially protected and certified environment, the PGEC. The PGEC also restricts the communication between the application and the service provider to what is explicitly allowed by the service user. In addition to those means, the PGEC also implements countermeasures against malicious attacks such as modified host systems and covert channel attacks, which might be misusing CPU load to signal data out of the PGEC. Thus, the PGEC guarantees a “one time use” of the provided private data.
This thesis describes the complete design of a low cost 60 GHz front end in SiGe BiCMOS technology. It covers the topics of a system plan, designs of building blocks, designs of application boards and real environment tests. Different LNA and mixer topologies have been investigated and fabricated. Good agreements between measurements and simulations have been achieved by using the self-developed component models. A transceiver front end system is built based on these blocks. A heterodyne architecture with a 5 GHz IF is adopted because it is compatible with the standard IEEE 802.11a, which allows the reuse of some existing building blocks of the 5 GHz transceiver. The transceiver chips are assembled onto application boards and connected by bond-wires. Bond-wire inductances have been minimized by using a cavity and compensated by an on board structure. The front end has been tested by both QPSK and OFDM signals in an indoor environment. Clear constellations have been measured. This was the first silicon based 60 GHz demonstrator in Europe and the second in the world.
It is predicted that, in the next years, wireless sensor networks could be massively deployed in a wide variety of application areas, such as agriculture, logistics, automation, or infrastructure monitoring. An extremely low power consumption, high dependability, and low cost are common requirements for sensor nodes in all these applications. This can be achieved only by tiny, power-efficient microcontrollers and communication systems integrated on a single chip. Formal description techniques, such as SDL (Specification and Description Language), are suitable to formally prove properties of models designed in these languages. Code generators facilitate the automatic transformation of SDL models into software implementations, while preserving the properties of the model and, thus, achieving high system dependability. The implementations consist of the translated state machine behavior and, additionally, require a run-time environment for model execution. The objective of this work was to investigate an integrated design flow for embedded systems, which should allow the development of efficient and dependable system implementations from abstract SDL specifications. In this thesis, concepts for minimal SDL run-time environment have been devised and realized by an example implementation. Not only pure software implementations should be considered, but starting from these also the hardware/software (HW/SW) partitioning of the system should be supported. For this purpose, a cosimulation framework that allows the coupling of an instruction set simulator (ISS) with a functional SDL simulation has been investigated and prototypically implemented within the scope of this thesis. By shifting functionality to dedicated hardware components it is possible to take computational load from the microcontroller and to decrease the overall energy consumption by reducing the clock frequency and lowering the supply voltage. Due to the use of SDL, the design flow lends itself particularly to the implementation of communication protocols, and is limited to applications with soft real-time requirements. For an SDL-based design flow targeted to resource-constrained embedded systems, concepts and real implementations of minimal SDL run-time environments were lacking. Available software tools, indeed, enable the transformation of SDL models into C code, however for an efficient implementation, an integration into existing real-time operating systems (RTOS) for small microcontrollers is essential. A prototypical implementation of a run-time library for the Reflex RTOS has been created to validate our general concepts. It is about 30 % faster and consumes less than half of the program memory compared to the operating system independent run-time environment of the tool vendor Telelogic. For simple SDL models, the application requires in total less than 8 kbytes program memory and 1 kbyte RAM. For the evaluation of design alternatives that realize different hardware/software partitionings, instruction set simulators are particularly suitable. They facilitate the identification of performance bottlenecks of the HW/SW system. Test stimuli are required in order to measure the performance and response time of systems under design. The development of an environment that generates such test signals can be a laborious task. Thus, it is reasonable, especially in the design of protocols, to use an SDL simulation of a communication network to generate these test stimuli. Such an SDL model already exists and is the basis for the implementation. The protocol implementation simulated by the ISS then becomes part of the network simulation. An efficient coupling of SDL simulations with instruction set simulators had to be investigated, and a solution is presented in this thesis. Based on the general concepts, a cosimulation framework for the ISS TSIM for the LEON2 processor was realized by the author. The joint SDL and instruction set simulation is very fast, which could be demonstrated by connecting a software implementation of the complex IEEE 802.15.3 medium access control (MAC) protocol with an SDL simulation of a network consisting of four devices. The real execution time for 10 seconds of simulation time amounted to just 50 seconds. The overall design flow was validated by means of a HW/SW implementation of the IEEE 802.15.3 wireless MAC protocol. The author designed a complete SDL model of the protocol and integrated it into Reflex. By using our cosimulation environment for the TSIM simulator, the model was partitioned into hardware and software. For the hardware part, a dedicated protocol accelerator was designed by the author. This hardware component was integrated on a single chip with the LEON2 processor and, finally, manufactured. It could be shown that the presented methodology enables the design and implementation of efficient HW/SW systems. Consequently, it can be applied to the development of dependable and energy-efficient wireless sensor nodes and other embedded systems.
During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.
This Dissertation is a contribution to the design of the Synchronization and Channel Estimation algorithms in Wireless OFDM systems, paying special attention to their implementation. After investigation of the main impairments affecting OFDM in a wireless transmission, the Dissertation obtains solutions for all the blocks forming the so-called Inner Receiver. The IEEE 802.11a standard is taken in this work as a reference, since this is the first standard proposal in which OFDM is applied for wireless LAN with transmission rates of up to 54 Mbps. The low-power feature of our proposals has been demonstrated by designing an Integrated Circuit fully compatible with the IEEE 802.11a specifications. Results show that the power figures expected for our design are very competitive in comparison with the results reported by other research groups and companies working in this field.