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In modern information technology, increasingly powerful electronic circuits are required for the targeted generation of complex signals with well-defined amplitudes and phases. In circuits of this type, oscillators frequently form the central element because of its phase noise and stability, which essentially determines the achievable precision in the signal generation. Further requirements are derived from the electronic definability of the signal properties and the operational behavior of the oscillators. Conventional oscillator circuit models autonomous circuits, mainly consist of a passive frequency-selective or phase-selective network and an active amplifier element, which together produce an oscillatory circuit via a suitable feedback. At first glance, the circuit topology seems to be quite simple, and can often be explained quite visibly. However, when it comes to describing in particular the very important phase noise dynamics and stability of oscillators, it very soon becomes apparent that highly complex structures are involved. A fundamental difficulty in the theoretical description arises due to the non-linear behavior of oscillators, the understanding of which is crucial for a reliable description of jitter and oscillator phase noise. The resonant condition of oscillators arises due to the fact that the noise in the oscillator circuit is always present in the system, which is amplified in a frequency-selective manner to the extent that a stable oscillation arises at most at a fixed frequency because of non-linear limitation of the amplification. The frequency selectivity arises due to the frequency selectivity or phase selectivity of the passive feedback path. The non-linear limitation of the amplification in the oscillator normally results in a very reliable control of the amplitude noise of the output oscillation. It is well understood that any particular oscillator’s phase noise could be improved by increasing the generated signal amplitude or increasing the quality factor of the resonant network. Increasing the signal level is limited by the utilized supply voltage or the break down limits of transistors and cannot be increased further to improve the phase noise. Accordingly, the remaining phase noise, which can normally be minimized via resonating circuits with pronounced phase selectivity and therefore a high quality factor resonator, is of great importance for oscillators. Traditional high Q-factor resonators (ceramic resonator, surface acoustic wave, bulk acoustic wave, dielectric resonator, YIG resonator, Whispering gallery mode resonator, Optoelectronic resonator, etc.) are usually 3-dimensional structures and bulky for both handheld and test-measurement equipments and does not offer integration using current foundry technology. The current and later generation wireless communication market is pushing the need for miniaturization to its limits. Printed coupled transmission line resonator is a promising alternative due to its ease of integration and compatibility with planar fabrication processes but limited by its large physical size and low quality factor, making it a challenging choice to design low phase-noise oscillators. This problem is more prominent in integrated circuits (ICs) where high degrees of thin conductor losses reduce the quality factor by orders of magnitude compared to hybrid circuit technologies.
This thesis describes the design and investigation of a variation of printed resonators using Möbius slow-wave and Metamaterial structures for the applications in oscillator circuits. A novel Möbius slow-wave mode-coupled structure offers additional degrees of freedom (higher Q-factor and multi-band characteristics for a given physical size) as compared to conventional transmission line printed resonators. A design study has been carried out to optimize the phase noise performance by using the novel resonant structures (mode-coupled, slow-wave, Möbius strips, evanescent mode, negative index material-Metamaterial) in conjunction with mode locking and injection locking for improving the overall performances, beyond the limits imposed by conventional limitations. The thesis also covers a broad spectrum of research on DRO and OEO ranging from practical aspects of circuit implementation and measurement, including the modeling of optical fiber delay line used as a thermally stable high Q-factor resonator structure. This thesis is research work carried out from 2004-2014, organized in 11 chapters, theoretical and experimental results documented by a range of specific measurement results and substantiated by over 200 scientific publications over dozen patents. The Metamaterial Möbius technology discussed in this thesis can open new era in the field of imaging, sensors, cloaking, energy harvesting and energy efficient microwave circuit and system Solutions.
The thesis addresses the design of monolithically integrated radio frequency amplifiers for X-band applications. The focus is on low-voltage low-noise amplifiers and efficient power amplifiers with high output power level. The challenge here is to realize stable amplifiers with remarkable performance metrics at low supply voltages. The general approach for stabilization amplifiers in the above frequency range is the use of a cascode topology which, however, requests higher supply voltages then single transistor operation. By using a special passive frequency-selective feedback, the use of the cascode topology could be avoided, and the amplifiers are stabilized over the entire frequency spectrum. Simultaneously, this feedback is used to neutralize the intrinsic feedback of the transistor at operating frequencies. As a result, a frequency dependent performance degeneration of the transistor can be mitigated.
This work describes the influence of the passive frequency-selective feedback. Its usage as well its limitation are explained using the examples of a realized low noise amplifier and different power amplifiers. Further, the design of radio frequency amplifiers at X-band frequencies that employs silicon-germanium heterojunction bipolar transistors is described. All amplifiers were either incorporated in a 0.25 µm SiGe:C BiCMOS technology or in a 0.35 µm SiGe:C bipolar technology. The main achievements of this work include:
- A 8.7 GHz narrow-band low noise amplifier incorporated in a 0.35 µm SiGe bipolar technology. The noise figure is 2.2 dB and the gain 28 dB at a supply voltage of 3 V. The low noise amplifier was subsequently used for a design of a double-balanced I/Q mixer.
- Two packaged high efficient power amplifiers operating at a center frequency of 12 GHz. They are incorporated in a 0.35 µm SiGe bipolar technology. One amplifier uses a transformer-based output matching network and achieves 30.9 % of power-added efficiency and 23.9 dBm of maximum output power at a supply voltage of 1.8 V. The second amplifier utilizes an LC-balun for impedance matching at the output and a power-added-efficiency of 38 % at 1.8 V is measured. The maximum output power was 23.4 dBm.
- A power amplifier in a 0.35 µm SiGe bipolar technology that uses power combining techniques to achieve 30 dBm (1 W) and 30 % of power-added efficiency at 10 GHz and 2 V supply voltage.
- Two power amplifiers, incorporated in a 0.25 µm SiGe:C BiCMOS technology, demonstrating the capability of a non-advanced SiGe process to be used for radio frequency power applications. Power combining techniques, the use of the passive frequency-selective feedback and layout optimization enables the realization of power amplifiers which exhibit an output power of 30 dBm and a power-added efficiency of 35 % at supply voltages lower as 2.6 V.
Stetig steigende Leistungen der Leistungsverstärker in den Sender-Empfängermodulen zwingen den rauscharmen Verstärker zu einem immer höheren Schutz am Eingang. Aufgrund hoher Durchbruchspannungen bieten GaN HEMTs eine robuste Eingangsstufe, womit ein Schutz des LNA Eingangs und die damit verbundene Verschlechterung der Rauschzahl unnötig wird. Allerdings nützte dieser Schutz nicht allein den rauscharmen Verstärker, da nachfolgende Stufen durch die hohen Ausgangsleistungen der GaN LNAs zerstört werden können. Daher widmet sich diese Arbeit der Untersuchung von robusten rauscharmen GaN Verstärkern sowie verschiedener Schaltungen zum Schutz der nachfolgenden Stufen vor einer zu hohen Eingangsleistung, wobei die Rauschzahl unbeeinflusst bleiben soll.
Da eine robuste Eingangsstufe relevant für diese Arbeit ist, wurden neuartige Designs von robusten GaN LNA MMIC untersucht. Einerseits wurde ein LNA MMIC Chip mit einer gestapelten Eingangsstufe entwickelt, womit die Eingangsleistung und entsprechend die Robustheit erhöht werden konnte. In dieser Arbeit wird ein verbessertes Design des gestapelten GaN LNA MMIC vorgestellt, dessen Verstärkung von mehr als 23 dB und ein Rauschmaß von 2,6 dB im C-Band Frequenzbereich erreicht. Anderseits wurde ein neuartiger multiband GaN LNA MMIC für die Frequenzen 0,8 GHz; 1,8 GHz und 3,6 GHz entwickelt. Dieser erreicht eine Verstärkung von mehr als 29 dB bei 0,8 GHz und mehr als 34 dB bei 3,6 GHz mit einer maximalen Verstärkung von 34,9 dB bei 1,8 GHz sowie einen minimalen Rauschmaß von 2,2 dB bei 3,6 GHz. Der multiband LNA MMIC ist mit einen OIP3 von mehr als 36dBm bei 3,6 GHz hochlinear. Weiterhin wurde für den gestapelten und den multiband GaN LNA MMIC die Robustheit mittels eines hochohmigen Widerstands in der Gate Versorgung verbessert.
Im Rahmen der Charakterisierung von GaN Verstärkern zeigt sich, dass der Gate DC und Drain DC Strom Indikatoren jeweils für die Kompression und Sättigung der Ausgangsleistung im Überlastfall darstellen. Der Zusammenhang zwischen dem Gate DC Strom und dem Überlastfall war der Ausgangspunkt für die Entwicklung der Schaltungen zur Limitierung der Ausgangsleistung, um die nachfolgenden Stufen des LNAs zu schützen. Daher wird dieser Strom zum Schalten eines Ausgangsdämpfungsglieds sowie einer adaptiven Drain DC Versorgung verwendet. Das Ausgangsdämpfungsglied wurde als ein GaN HEMT in Common-Gate Konfiguration an den Ausgang eines robusten GaN LNAs auf einen Chip geschalten, wodurch im Überlastfall eine Dämpfung von 29 dB erreicht wird. Weiterhin konnte durch die adaptive Drain DC Versorgung, welche als eine hybride Schaltung mit einem robusten GaN LNA MMIC als Kern entwickelt wurde, eine Dämpfung von 28 dB erzielt werden. Sowohl für das Ausgangsdämpfungsglied als auch für die adaptive Drain DC Versorgung blieben die Kleinsignal Verstärkung und das Rauschmaß des GaN LNA MMICs unbeeinflusst.
With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors.
Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail.
In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.
The design of high Q oscillators, using Crystals at lower frequencies, (and dielectric resonators at much higher frequencies), has long been considered a black art. This may be due to the fact that a systematic approach with optimized design guideline for crystal oscillators could not be found after extensive literature search.
In this dissertation, after analyzing the first crystal oscillator by W.G. Cady (1921), other high performance crystal oscillators will be discussed, analyzed and calculated.
A single transistor crystal oscillator design as used by HP (Hewlett Packard) in one of their designs, the HP10811A is considered in this thesis for mathematical analysis and CAD (Computer aided Design) simulation. This was also measured on state-of-the-art signal source analyzer. After validation, this design is scaled to 100MHz, the frequency of interest for this dissertation.
Though most designers use a single transistor based oscillator circuit, it is not an optimized design because of limited control over key design parameters such as loop gain, dc current etc.
This dissertation is an attempt to overcome the limitation due to the single transistor circuit and to give a step by step procedure, explaining the significance of a two transistor design with thorough analysis and design simulation results. This two stage transistor circuit is also not yet a best solution in terms of phase noise performance and output power, and some add-on circuitry will be needed for an optimized performance.
An important contribution of this work is to show that since the voltage gain is the ratio of the collector resistor and the emitter resistor, the performance is practically independent of the VHF transistor and gives better control over various parameters of the oscillator, in order to optimize the design.
A grounded-base amplifier is then introduced and added for improving the isolation and the output power. Unlike most oscillators, that take the output from the collector, a novel concept introduced by Rohde [14], is incorporated here, where the crystal is used as a filter that is then connected to the grounded base amplifier, a technique which many companies have been using. This dissertation will show that this technique increases the output power without significantly affecting the phase noise. Such a validation is needed for better understanding and as per my knowledge, has not been done so far.
For the oscillator, the tuning diode sensitivity and flicker noise contribution are also taken into consideration, by calibrating the mathematics and its validation is shown.
Crystal resonators of the type AT and stress-compensated (SC) cut devices will be considered as they give the best performance. The one port Colpitts type oscillator is considered first and the two port two transistor design later. Both will need a post amplifier/buffer stage.
A complete step by step design procedure for an optimized 100MHz crystal oscillator is then presented.
For completeness, CAD Simulation and Experimental results are provided for 10 MHz, 128 MHz and 155 MHz VCO circuits.
This dissertation presents a novel technique for enhancing the spurious-free dynamic range of radio monitoring receivers with a bandwidth of several gigahertz. The improvement is based on suppressing the discrete spurious signals that occur at higher drive levels in the output spectrum of the required broadband analog-to-digital converter. The achievable improvement of the spurious-free dynamic range is typically more than 20 dB, allowing better, gap-free monitoring of wide frequency ranges. The attenuation of the spurious signals is achieved by a unique combination of two separate analog-to-digital converters working in parallel and subsequent digital signal processing. The developed solution is not limited to broadband radio monitoring receivers but can generally suppress certain types of spurious signals generated during analog-to-digital conversion.
Although GaN HEMTs are regarded as one of the most promising RF power transistor technologies thanks to their high-voltage high-speed characteristics, they are still known to be prone to trapping effects, which hamper achievable output power and linearity. Hence, accurately and efficiently modeling the trapping effects is crucial in nonlinear large-signal modeling for GaN HEMTs.
This work proposes a trap model based on an industry standard large-signal model, named Chalmers model. Instead of a complex nonlinear trap description, only four constant parameters of the proposed trap model need to be determined to accurately describe the significant impacts of the trapping effects, e.g., drain-source current slump, typical kink observed in pulsed I/V characteristics, and degradation of the output power. Moreover, the extraction procedure of the trap model parameters is based on pulsed S-parameter measurements, which allow to freeze traps and isolate the trapping effects from self-heating. The model validity is tested through small- and large-signal model verification procedures. Particularly, it is shown that the use of this trap model enables a dramatical improvement of the large-signal simulation results.
The dissertation covers the physical, design, simulation and measurement aspects of extremely high Q precision oscillators for space applications. Existing design approaches and methods are evaluated, and it is shown that only physically complete models can deliver a good agreement between theory and experiments. A prototype was built showing very good phase noise and stability.
This work addressed the challenges of accurate mm-wave characterization of devices fabricated in advanced semiconductor technologies. It developed the in-situ calibration solution that is easy to be implemented for silicon technologies. The new technique was verified up to 110 GHz on three difference processes: high performance SiGe:C BiCMOS from IHP Microelectronics (Germany), BiCMOS9MMW from STMicroelectronics (France), and RF CMOS 8SF from IBM Microelectronics (USA). The measurement frequency was solely limited by the capability of the test equipment. Practical results demonstrated that proposed in-situ calibration significantly outperforms the convention method independently on the process specifics and complexity. Some important aspects of the on-wafer S-parameter measurement assurance were presented as well. The discussion included the analysis of the calibration residual errors caused by the improper boundary conditions of coplanar calibration standards and the impact of the RF probe tip design. In conclusion, some suggestions for further accuracy improvement of the proposed method are given.
Untersuchung und Optimierung robuster und hochlinearer rauscharmer Verstärker in GaN-Technologie
(2018)
Die nächste Generation von integrierten Sende- und Empfangsystemen erfordert sowohl robuste rauscharme Verstärker als auch Leistungsverstärker auf einem einzelnen Chip. Die GaN-HEMT-Technologie hat bisher gezeigt, dass sie durch ihre hohen Durchbruchspannungen, die hohe Elektronenbeweglichkeit und die niedrige Rauschzahl ein guter Kandidat für die Realisierung solcher Systeme ist.
Diese Arbeit beschäftigt sich mit hochlinearen und robusten rauscharmen Verstärkern, welche in Sender-Empfänger-Systeme integriert werden können. Zuerst wird der GaN HEMT charakterisiert. Die Eigenschaften von Transistoren werden während des Burn-in Prozesses und gepulster Anregung mit hoher Überlast am Eingang analysiert. Damit werden die Grundlagen für das Verständnis des Verhaltens eines Verstärkers während und nach der Übersteuerung am Eingang gelegt.
Der Hauptteil dieser Arbeit zeigt die Entwicklung und die Charakterisierung von robusten rauscharmen Verstärkern. Darüber hinaus wird ein neues Konzept für die Steigerung der Robustheit entwickelt, gemessen und charakterisiert.
Das Konzept verwendet eine neuartige Zusammenschaltung zweier
Transistoren am Verstärkereingang, wodurch die Spannungsfestigkeit gegenüber hohen Leistungspegeln gesteigert wird. Damit konnten Höchstwerte von +44dBm mit CW-Anregung und +47dBm mit gepulster Anregung am Verstärkereingang ohne Beschädigung demonstriert werden.