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With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors.
Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail.
In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.
The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP). Clock synthesis and the synchronization of systems on the scale of large experimental detectors is an important aspect of their successful implementation and a necessity for achieving their anticipated performance. Developments in this area to increase radiation tolerance and performance are motivated by emerging requirements for clock generation and distribution.
The thesis reviews the requirements of existing and emerging systems with regards to radiation-tolerant clock generation. To characterize clock generation circuits and adequately assess their conformity with the identified requirements in radiation tests, a number of methods and instrumentation setups are developed and characterized. The presented approaches combine aspects of digital programmable logic, analog circuit design and and digital signal processing concepts.
To address design challenges in deep submicron CMOS nodes, the design of radiation-tolerant all-digital PLL and CDR circuits is explored in this thesis. These circuits promise opportunities to improve the radiation tolerance of clock generators, and hence this thesis devises the design of a radiation-tolerant ADPLL/CDR circuit compatible with requirements of high energy physics (HEP) electronics. Using radiation testing, the sensitivity of the circuits is studied and mitigation strategies for identified limitations are discussed. Three such ADPLL/CDR circuits are developed and tested in the form of macro blocks targeting applications in frontend ASICs for high energy physics. The circuits demonstrate jitter performance, power efficiency and radiation tolerance comparable to or better than currently used conventional PLL circuits.
As a final aspect, the improved testing instrumentation and methodology developed within this thesis is applied to uncover a previously unrecognized radiation sensitivity in a conventional, radiation-hardened clock generator circuit. An integrated planar on-chip inductor is experimentally identified as responsible for this sensitivity. Irradiation tests are performed to study and characterize the nature of this sensitivity. The results suggest that energy deposition, likely within dielectric materials surrounding the inductor wiring, alters the inductor's terminal impedance. This stimulates frequency errors with long recovery times in the oscillator. The manifestation of this effect in HEP radiation environments is studied using proton irradiation, where a mitigation strategy is experimentally validated. A reduction of the impact of this sensitivity is demonstrated. To help conclusively identifying the underlying mechanism responsible for the sensitivity within the inductor itself, further research opportunities are suggested.
Die vorliegende Dissertation setzt ein empfangssignalstärkebasiertes, probabilistisches, zweistufiges Ortungsverfahren zur symbolischen Lokalisierung von Objekten im Indoor-Bereich um. Dazu wird eine Hardware auf Basis der im 2,4 GHz ISM-Band arbeitenden Funktechnologie der Firma Nanotron zum Aufbau eines unidirektionalen Funknetzes entwickelt. Es besteht aus mobilen und stationären Netzwerkknoten und wurde in verschiedenen Umgebungsszenarien getestet. Neben dem für den Ortungsalgorithmus erforderlichen Signalstärkeparameter (AGC-Gain) wird ebenso die Sendeleistung als weiterer Systemparameter variiert. Die dadurch erweiterte Datenbasis vergrößert die Trennschärfe der diskreten a posteriori-Verteilung. Deren Modalwert bestimmt den geschätzten Aufenthalt des Mobilknotens im diskreten Raum. Der innerhalb einer ausgewählten Gebäudestruktur angewendete Basisalgorithmus liefert eine absolute Ortungsgenauigkeit von circa 73% und bestätigt so die prinzipielle Eignung des Verfahrens. Der mittlere Entfernungsfehler liegt für das 95. Perzentil bei 6,2 m. Bei einer mittleren Zellengröße von 5x5 m wird damit selbst im Fall einer Fehlortung mit hoher Wahrscheinlichkeit eine unmittelbare Nachbarzelle ausgewählt. Der flexible Aufbau erlaubt zusätzliche Untersuchungen an Parametern, welche Einfluss auf die Ortungsgenauigkeit haben. Darunter zählen Variationen der Höhe und Antennenausrichtung der Mobilknoten sowie Untersuchungen zur Hardwarestreuung. Dabei wird deutlich, dass in den beiden erstgenannten Fällen eine deutliche Verringerung der Trefferquote bis hin zu 37% auftritt. Hingegen belegt die hohe Reproduzierbarkeit der Ortungsgenauigkeit bei Verwendung baugleicher Netzwerkknoten die Übertragbarkeit einer mit einem Mobilknoten erstellten RadioMap auf andere Knoten. Das Ortungsverfahren wird neben dem primären Einsatzfeld im Indoor-Bereich ebenfalls im Outdoor-Bereich getestet. Dabei können Interferenzerscheinungen durch Mehrfachsignalausbreitung gesondert untersucht und modelliert werden. Im Anschluss werden Ansätze vorgestellt, welche das System unter verschiedenen Gesichtspunkten wie der Verringerung der erforderlichen Speicherkapazität, der Verringerung der Rechenzeit durch Eingrenzung des Suchraumes sowie die Erhöhung der Ortungsgenauigkeit durch verschiedene Filterstrukturen erweitern. In deren Ergebnis können die erforderliche Speicherkapazität um 93% gesenkt, die Rechenzeit um 42% verringert und die absolute Ortungsgenauigkeit auf 83% gesteigert werden. Die Arbeit schließt mit einer Diskussion der Ergebnisse und gibt Ausblicke auf aufbauende Forschungsschwerpunkte.
With further scaling of CMOS technology noise disturbance, mismatch and process variation become the major constraints of analog DC-DC converters. Consequently, digitally assisted DC-DC converters are coming in the focus of new systems, because they are easier to be configurated in the applications than the typical analog DC-DC converters, while being more robust against noise disturbance and process variation.
As interface devices between analog real world and digital signal processing, ADCs must be optimized for signals in digital DC-DC converters. But the existing synchronous ADCs, which require multiple clock cycles per conversion, as SAR and Pipeline ADCs, are not suitable for the application in DC-DC converters because of special signal characteristics. For stability reasons the digital feedback control in DC-DC converters requires a short group delay (dead time). So synchronous ADCs must be run at a sampling frequency as high as possible. But this approach results unfortunately in high power dissipation.
Compared to the above mentioned ADCs, the delta-encoded or Tracking ADC exhibits the shortest group delay by performing the data conversion only in one clock cycle. It makes the digital feedback control of DC-DC converters possible to response the output exactly and simultaneously. However, the synchronized Tracking ADC still has to cover the double of broad signal bandwidth of disturbance, which appears at the output of DC-DC converters occasionally, dissipating unnecessary excessive power.
This dissertation presents a new concept of Tracking ADC that selfadjusts the conversion rate depending on the slope of the input signal. For a slowly varying input, this Tracking ADC is self-clocked at a low frequency in normal mode, but once the signal varies fast and the slope exceeds a defined threshold, the conversion rate of the ADC is increased to track the signal accurately. By using the proposed solution not only the issue of input slope overload for typical Tracking ADCs is significantly improved, but also the average sampling rate is decreased. Therefore, the power dissipation of the proposed ADC is also reduced.
As a proof of this concept, a 6-bit Tracking ADC with transient-driven self-clocking is implemented in 0.13μm CMOS technology. The prototype of the ADC occupies an area of 400μm×200μm. The maximum power dissipation is 84μW at a supply voltage of 1.4V, when operated at 50MS/s. The integral nonlinearity (INL) is better than 0.5LSB, and the effective number of bits (ENOB) at the sampling frequency of 12.5MHz is 4.4 bits, where the ideal ENOB is limited to 5 bits for 6-bit Tracking ADCs.
Voltage controlled oscillators are commonly realized using varactor diodes in order to tune the resonator frequency. The drawback in practical implementation is the relatively high cost of the diodes, and the large space required for the inductors. Replacing the inductors by active tunable inductors would solve these issues and open a path for cost-effective small integrated oscillator designs. In the past, active-inductor approaches were not competitive due to the high phase noise inherent to the active inductor. This work investigates active inductor oscillators, and presents a novel approach that yields low phase-noise VCOs. The theoretical investigations are verified by measurements of demonstrator circuits.