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Since electronics started to scale down, a growing concern about the reliability of these electronic devices has emerged. At the same time, the increased demand for high performance within the safety- and mixed-critical domains, such as the aerospace and automotive industry, motivated a shift from previous consolidated and mature technology to the new cutting edge devices with smaller feature sizes. Therefore, there is a need to improve the fault tolerance of these high-end devices so that minimum failure rates can be obeyed. Although redundancy has been a great solution for these problems, their drawbacks such as power and area overheads must be watched carefully, so that per-unit price does not extrapolate affordable limits, and the redundancy does not add more sources of error than it improves the fault tolerance. This thesis proposes an approach for run-time management of redundancy among the processor internal Functional Units (FUs) within mixed-critical scenarios, tackling the compensation of the trade-offs between fault-tolerance, power consumption, hardware usage (ageing), and hardware area (cost).
With these objectives in mind, this thesis presents a concept for a dynamic processor architecture capable to enable and disable redundancy of FUs on-demand, and a software mechanism for criticality-aware management of these units for mixed-critical processes within an Operating System (OS). For this purpose, a processor design was extended with a few additional instructions that enabled different replication schemes in the processor at run-time. Furthermore, a compatible Real-Time Operating System (RTOS) is also extended to enable the desired criticality-aware management of units.
Evaluating the implemented test platform when the extended processor was running bare-metal code, the latency to shift between different replication schemes was of only one instructions cycle. Furthermore, when the processor was running the adapted RTOS, the run-time overhead over the latency to switch between processes remained below 2.5%. Meanwhile, resulting from the processor extensions, the hardware overhead remained smaller than standard full core replication schemes such as core lock-step approaches. Regarding fault tolerance, the expected failure rate of the FUs module decreased by approximately 80% when its FUs were configured with Triple Modular Redundancy (TMR). Furthermore, when considering the whole area of the processor core, its respective failure rate decreased by about 15% when configured these units with the same triplication scheme. Finally, it is also presented that the run-time management of FUs was likewise able to decrease the power consumption and hardware ageing for the proposed mixed-critical scenario. After all, we can say that the concept can increase fault tolerance on-demand of a processor design with moderately low hardware overhead, while it also minimises the power consumption and hardware usage (ageing) for its intended mixed-critical scenario.
Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.