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The thesis addresses the design of monolithically integrated radio frequency amplifiers for X-band applications. The focus is on low-voltage low-noise amplifiers and efficient power amplifiers with high output power level. The challenge here is to realize stable amplifiers with remarkable performance metrics at low supply voltages. The general approach for stabilization amplifiers in the above frequency range is the use of a cascode topology which, however, requests higher supply voltages then single transistor operation. By using a special passive frequency-selective feedback, the use of the cascode topology could be avoided, and the amplifiers are stabilized over the entire frequency spectrum. Simultaneously, this feedback is used to neutralize the intrinsic feedback of the transistor at operating frequencies. As a result, a frequency dependent performance degeneration of the transistor can be mitigated.
This work describes the influence of the passive frequency-selective feedback. Its usage as well its limitation are explained using the examples of a realized low noise amplifier and different power amplifiers. Further, the design of radio frequency amplifiers at X-band frequencies that employs silicon-germanium heterojunction bipolar transistors is described. All amplifiers were either incorporated in a 0.25 µm SiGe:C BiCMOS technology or in a 0.35 µm SiGe:C bipolar technology. The main achievements of this work include:
- A 8.7 GHz narrow-band low noise amplifier incorporated in a 0.35 µm SiGe bipolar technology. The noise figure is 2.2 dB and the gain 28 dB at a supply voltage of 3 V. The low noise amplifier was subsequently used for a design of a double-balanced I/Q mixer.
- Two packaged high efficient power amplifiers operating at a center frequency of 12 GHz. They are incorporated in a 0.35 µm SiGe bipolar technology. One amplifier uses a transformer-based output matching network and achieves 30.9 % of power-added efficiency and 23.9 dBm of maximum output power at a supply voltage of 1.8 V. The second amplifier utilizes an LC-balun for impedance matching at the output and a power-added-efficiency of 38 % at 1.8 V is measured. The maximum output power was 23.4 dBm.
- A power amplifier in a 0.35 µm SiGe bipolar technology that uses power combining techniques to achieve 30 dBm (1 W) and 30 % of power-added efficiency at 10 GHz and 2 V supply voltage.
- Two power amplifiers, incorporated in a 0.25 µm SiGe:C BiCMOS technology, demonstrating the capability of a non-advanced SiGe process to be used for radio frequency power applications. Power combining techniques, the use of the passive frequency-selective feedback and layout optimization enables the realization of power amplifiers which exhibit an output power of 30 dBm and a power-added efficiency of 35 % at supply voltages lower as 2.6 V.
The goal of this thesis is the analysis of the challenges and finding solutions for the design of mm-wave transceivers. The work presented here is focused on design of transmitter (TX) components, which are critical for the performance of the whole analog front-end. Phase-locked loop (PLL) phase noise is optimized, an image-rejection filter and a high 1 dB compression point (P1dB) power amplifier (PA) are designed. The PLL phase noise optimization is presented and different PLL topologies are compared. A new optimized recipe for calculating PLL parameters of a forth order PLL is presented. Using this approach the spurious sidebands can be reduced by up to 10 dB. The image-rejection filter chapter analyzes the challenges related to the design of the integrated image–rejection filter. The analysis presented here is the first on integrated filters for the 60 GHz band, because the previously published work dealt with on-board filters. The main problems related to the design of integrated filters arise from the low quality factor of the integrated resonators. The effects are high insertion loss and low selectivity. Two measures to reduce the insertion loss of the image–rejection filters were suggested. One is to design the filter as broadband. This measure deteriorates selectivity, so the minimum required image–rejection will limit the width of the passband. The second measure is to design the filter as broadband with non-equidistant transmission zeros (i.e. asynchronously tuned filter). This measure will improve both the insertion loss and the image–rejection. The challenges related to the design of mm-wave PAs with high P1dB are analyzed and the procedure of the PA design is presented. The difficulties related to the PA design and layout are discussed and optimum solutions presented. Limits of different power combining techniques for integrated PAs are discussed. Effects of poor on-chip ground connection are analyzed. Different causes for P1dB degradation are analyzed. The produced PA features a differential cascode topology. The layout is symmetrical and presents a virtual ground on the symmetry line for the differential signal. The optimized schematic and a symmetrically drawn layout resulted in a 17 dBm measured P1dB. It was the highest reported P1dB in 60 GHz SiGe PAs when it was published. The fully integrated TX was used for data transmission with data rate of 3.6 Gbit/s (with coding 4.8 Gbit/s) over 15 meters. This is the best result in the class of 60 GHz AFEs without beamforming.
During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.
In der Arbeit wird untersucht, inwieweit zwei Epitaxieverfahren (LPCVD- und RPCVDVerfahren) geeignet sind, Bor-dotierte Si/SiGe/Si-Heteroschichtstapel mit guter Homogenität und Reproduzierbarkeit herzustellen. Die Bewertung der Epitaxieverfahren erfolgte anhand von HBT-Parametern, deren Streuungen von Wafer zu Wafer und über den Wafer ermittelt und mit publizierten Referenzdaten des etablierten UHVCVD-Verfahrens verglichen wurden. Die besten Ergebnisse wurden für RPCVD-basierte Si/SiGe/Si-Schichstapel ermittelt. Schichtstapel beider Epitaxieverfahren haben eine geringe Dichte elektrisch aktiver Defekte. Als kritischer Epitaxieprozeßparameter wurde die Abscheidetemperatur ermittelt. Im Fall des LPCVD-Verfahrens hat die Trägergasgeschwindigkeit einen großen Einfluß auf die Homogenität des Boreinbaus. Mit dieser Arbeit wurde nachgewiesen, daß das RPCVDEpitaxieverfahren eine Alternative zum etablierten UHVCVD-Verfahren ist.