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Real100G.COM
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In 2012 a group of researchers proposed a basic research initiative to the German Research Foundation (DFG) as a special priority project (SPP) with the name: Wireless 100 Gbps and beyond. The main goal of this initiative was the investigation of architectures, technologies and methods to go well beyond the state of the art. The target of 100 Gbps was set far away from the (at that time) achievable 1 Gbps such that it was not possible to achieve promising results just by tuning some parameters. We wanted to find breakthrough solutions. When we started the work on the proposal we discussed the challenges to be addressed in order to advancing the wireless communication speed significantly. Having the fundamental Shannon boundary in mind we discussed how to achieve the 100 Gbps speed.
The requirement for wireless communication with a speed beyond 100 Gbps is growing. There are mainly two possible approaches to achieve 100 Gbps system. One approach is to target lower transmission bandwidth and very high spectral efficiency. This method requires advanced digital signal processing operations, which are power-hungry. Another possible path is to go for a high-transmission bandwidth and a moderate spectral efficiency. We decided for this direction to implement a 100 Gbps system. We have chosen parallel sequence spread spectrum (PSSS) as an analog-friendly mixed-signal modulation where most of the baseband processing is in the analog domain, and only a small part is in the digital domain. For the channel equalization, we consider an “effective channel” that takes into account the wireless channel and the effects of the transmitter and receiver hardware impairments. The influence of the nonlinear channel response was analyzed for a PSSS modulated signal by employing the RAPP model for the power amplifier. For the first time, we performed a Hardware-In-The-loop experiment using PSSS modulation in the terahertz band. A PSSS modulated signal at a chip rate of 20 Gcps with spectral efficiency of 4 bit/s/Hz is transmitted using a 230 GHz RF-frontend operating in the linear range to achieve a data rate of 80 Gbps. One more important property is that the channel estimation and equalization are performed in the analog domain. A high-speed channel equalization algorithm was developed and implemented on FPGA/ASIC, which operates at(1/10)th of PSSS symbol rate. A parallel PSSS encoder transmitter architecture was designed to work at a high chip rate, and it was implemented on FPGA /ASIC and had an energy efficiency of 0.21 pJ bit−1 on 28nm ASIC.
In this Thesis, we put forward a case for the analog-friendly modulation scheme called PSSS. This scheme does not only modulates the signal but rather builds up an eco-system (such as channel estimation, equalization, and synchronization), which is responsible for the baseband operation.