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The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP). Clock synthesis and the synchronization of systems on the scale of large experimental detectors is an important aspect of their successful implementation and a necessity for achieving their anticipated performance. Developments in this area to increase radiation tolerance and performance are motivated by emerging requirements for clock generation and distribution.
The thesis reviews the requirements of existing and emerging systems with regards to radiation-tolerant clock generation. To characterize clock generation circuits and adequately assess their conformity with the identified requirements in radiation tests, a number of methods and instrumentation setups are developed and characterized. The presented approaches combine aspects of digital programmable logic, analog circuit design and and digital signal processing concepts.
To address design challenges in deep submicron CMOS nodes, the design of radiation-tolerant all-digital PLL and CDR circuits is explored in this thesis. These circuits promise opportunities to improve the radiation tolerance of clock generators, and hence this thesis devises the design of a radiation-tolerant ADPLL/CDR circuit compatible with requirements of high energy physics (HEP) electronics. Using radiation testing, the sensitivity of the circuits is studied and mitigation strategies for identified limitations are discussed. Three such ADPLL/CDR circuits are developed and tested in the form of macro blocks targeting applications in frontend ASICs for high energy physics. The circuits demonstrate jitter performance, power efficiency and radiation tolerance comparable to or better than currently used conventional PLL circuits.
As a final aspect, the improved testing instrumentation and methodology developed within this thesis is applied to uncover a previously unrecognized radiation sensitivity in a conventional, radiation-hardened clock generator circuit. An integrated planar on-chip inductor is experimentally identified as responsible for this sensitivity. Irradiation tests are performed to study and characterize the nature of this sensitivity. The results suggest that energy deposition, likely within dielectric materials surrounding the inductor wiring, alters the inductor's terminal impedance. This stimulates frequency errors with long recovery times in the oscillator. The manifestation of this effect in HEP radiation environments is studied using proton irradiation, where a mitigation strategy is experimentally validated. A reduction of the impact of this sensitivity is demonstrated. To help conclusively identifying the underlying mechanism responsible for the sensitivity within the inductor itself, further research opportunities are suggested.
Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.
The reliability of interconnects on integrated circuits (IC) has become a major problem in recent years because of the rise of complexity, the low-k-insulating material with reduced stability, and wear-out-effects from high current densities. The total reliability of a system on a chip is increasingly influenced by the reliability of the interconnections, which is caused by increased communication from the elevated number of integrated functional units. In recent years, studies have predicted that static faults will occur more often decreasing the reliability and the mean time to failure. The most published solutions aim to prevent dynamic faults and to correct transient faults. However, built-in self-repair (BISR) as a solution for static faults has not previously been discussed along with the other possible solutions. Theoretically, BISR can lead to higher reliability and lifetime. This is my motivation to implement BISR for integrated interconnects. Because BISR cannot repair transient and dynamic faults, I combine BISR with other approved solutions in this thesis. The results show that the combination leads to higher reliability and lifetime with less area and static power overhead compared to the existing solutions.
In this work a compact, monolithically integrated, high frequency sigma-delta phase-locked loops (PLLs) designed in 0.13 μm CMOS technology are investigated. The research focuses on the analysis of PLL spurious performance degradation caused by the integrated digital sigma-delta modulator, design and optimization of compact sigma-delta modulators with improved tonal and switching noise performance. The main achievements of this work include: 1. An implementation of MASH (multistage) modulator in the dual edge triggered style is proposed. The implementation offers two advantages over conventional MASH when integrated into the same die with a fractional-N PLL: 1) the modulator’s area is reduced by 15–20%; 2) the switching noise power is distributed in such a manner, that the first reference spur of a synthesizer is not degraded; instead, the glitch energy is shifted to the second multiple of reference frequency; in the work a benefit of such reference spur power distribution is demonstrated. Proposed implementation does not affect logical behavior of the MASH modulator. 2. MASH 1-1-1 (three stages of first order each) sigma-delta modulator with DC dithering used for frequency synthesis applications is investigated. At the expense of minimum additional hardware such dithering topology allows to shift tones to the low frequencies and decrease their power. 3. An oscillator-based dither generator is proposed for the use in MASH 1-1-1 modulator. The generator consumes less current and area, produces much less supply switching noise than a conventional pseudo-random dither generator while keeping modulator’s output free of tones. An empirical study of oscillator-based dither generator is presented. 4. MASH 1-1-1 modulator with direct feedback dithering is investigated. Such dithering topology requires no additional hardware to be implemented. Among the disadvantages of the direct feedback dithering is the addition of small DC offset to the output of MASH modulator and presence of some low power tones in amplitude spectrum. Two fully integrated 11 GHz sigma-delta PLLs incorporating single- and dual edge triggered MASH modulators with different dithering topologies were fabricated in 0.13 μm CMOS process. Spurious, as well as phase noise performance of the PLLs for different modulator topologies was compared. The PLL controlled by the integrated dual edge triggered MASH 1-1-1 modulator exhibited first reference spur below –66 dBc over the whole locking range and fractional spurs power not exceeding –70 dBc within 70% of the division ratio range.