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Due to the unique electronic band structure, graphene has opened the great potential to extend the functionality of a large variety of graphene-based devices in health and environment, energy storage, or various microelectronic applications, to mention a few. At this point, the implementation of graphene into Silicon (Si) semiconductor technology is strongly dependent on several key challenges. Among them, high-quality and wafer-scale graphene synthesis on CMOS compatible substrates is of the highest importance. Though large-area graphene can be achieved on substrates like copper, platinum, silicon carbide, or single-crystal Ni, however, high growth temperatures, unavailability of large scale, or contamination issues are the main drawbacks of their usage. In this PhD work, 8-inch scale graphene synthesis is attempted on alternative substrates such as epitaxial Germanium on Si and polycrystalline Nickel on Si. To achieve the growth of the highest quality of graphene, this work focuses on the investigations of various nucleation and growth mechanisms, substrate–graphene interfaces, effects of different substrate orientations, and detailed microscopic and macroscopic characterization of the grown films. Finally, it should also be stressed that the experiments in this work were carried out in a standard BiCMOS pilot-line, making this study unique, as its results might directly pave the way to further graphene integration and graphene-based device prototyping in mainstream Si technologies.
Within this work, the growth of out-of-plane Si and SixGe1-x and in-plane Ge nanowire have been investigated. For this purpose, nanowires have been grown ccording to the vapor-liquid-solid mechanism by means of molecular beam epitaxy with Au as metallic solvent on Si(111) and nano-structured Si(001)/SiO2 substrates. Each stage from surface preparation to final nanowire growth has been examined in order to determine relevant parameters which influence the nucleation process nanowire elongation. Particular attention has been given to describe the variation of Au droplet size distribution on Si(111) to evaluate the subsequent nanowire growth and to obtain optimal growth conditions for an site-selective nucleation on the nano-structured substrates.
Due to increased surface diffusion velocity with raising temperature, the droplet diameter distribution shifts from a positive skewed distribution with a high fraction of smaller droplets to a negative skewed distribution with a high fraction of larger droplets. The temperature dependency of the most probable droplet diameter and the number of Au droplets per area has been determined, which can be applied to predict the resulting nanowire diameters.
The out-of-plane Si and SixGe1-x on Si(111) predominantly grow along the surface normal, exhibiting the characteristic sawtooth-like sidewall faceting. During the nanowire formation, the Au surface diffusion velocity increased and causes an increase of the most frequently observed diameter. Furthermore, the total number of droplets/nanowires decreases by a constant factor due to an increase of the contact angle during Si/Ge deposition. The specific diameter range for an possible nanowire formation is reduced by the incorporation of Ge into SixGe1-x nanowires.
To obtain a regular and uniform nanowire growth, a nano-structured substrate consisting of Si(001) terminated pillars surrounded by a SiO2 matrix has been utilized. The initial growth of Ge nanowire starting from Si-Au droplets with SixGe1-x nucleation from ternary alloy is discussed from a thermodynamic point of view and a model based on the Si-Ge-Au ternary phase diagram has been developed to predict the SixGe1-x concentration gradient in the nanowire base. The fully relaxed in-plane Ge nanowires occur within one of the four distinct in-plane ⟨110⟩ directions and nanowires are mainly bounded by two 55° inclined {111} facets and a less pronounced planar (001) top facet.
High-resolution scanning X-ray diffraction microscopy reveals a slightly tilted growth of individual nanowires with respect to each other, causing an abrupt change in the orientation at junction points of interconnected nanowires.
Over the past seven decades Si microelectronics have developed rapidly. The success of the growing microelectronic industry is also caused by the expansion of materials in addition to Si. Open challenges are the monolithic integration of group IV devices on Si photonics as well as overcoming the size mismatch between electronic parts in the nm range and photonic parts in the µm scale. In this thesis the future application of GeSn NIs on Si as a photodetector is evaluated. The key element required for high performance optoelectronic devices is the formation of high-quality GeSn nano-islands (NIs), i.e. overcoming growth challenges such as introduction of defects due to lattice and thermal mismatch between GeSn and Si substrate as well as suppression of Sn precipitation caused by the limited solid solubility of Sn in Ge. To achieve high-quality nanostructures, the selective growth of GeSn NIs on Si(001) seeds via molecular beam epitaxy is investigated, exploiting the advantages of nanoheteroepitaxy (NHE), i.e. growth on nano-patterned substrates. The best compromise between selective growth of GeSn on Si nano-pillars at significant higher growth temperature than the eutectic temperature of GeSn and the incorporation of Sn into the Ge lattice was achieved at 600°C. X-ray diffraction studies confirmed the substitutional incorporation of 1.4at.% Sn into the NIs avoiding considerable Si interdiffusion from the substrate. Transmission electron microscopy images have shown that dislocations and stacking faults caused by plastic relaxation of the GeSn NIs are located near the NIs/substrate interface and thus, dislocation-free GeSn NIs can be formed, due to gliding out of the threading arms triggered by the NHE approach.
The high crystal quality of the GeSn NIs, enables the investigation of the bandgap by μ-photoluminescence (PL) analyses, demonstrating the shrinkage of the direct bandgap with increasing Sn content in the quasi-direct semiconductor.
All NIs however feature a β-Sn droplet on their nano-facets. To suppress the out-diffusion of Sn and hence increase the Sn concentration of the GeSn alloy, the GeSn NIs were overgrown with a thin Ge cap layer. The Ge cap successfully hinders the formation of Sn segregates on top of the NIs. Capping at 600 °C and 650°C results in an enrichment of Sn at the surface, forming a GeSn crust with 8±0.5at.% Sn. This wetting layer both enhances the optoelectronic properties of the NI core and exhibits a relatively strong PL emission attributed to direct radiative recombination.
Finally, a first demonstration of a GeSn NIs based photodetector was successful, due to the utilization of Al nano-antennas exhibiting an enhanced light coupling into the GeSn NIs at a wavelength of 700nm. The responsible mechanisms is the local plasmonic field enhancement of the incoming light. The manipulation of the resonance wavelength into the telecommunication regime, i.e. >1550nm, have to be investigated in future studies.
Um die technischen Limitierungen bezüglich der Geschwindigkeit und Verlustleistung aktueller Mikroprozessoren zu überwinden, sind neue Technologien notwendig. Eine Möglichkeit ist der Austausch klassischer metallischer Verbindungsleiter durch optische Übertragungswege. Als monolithisch integrierbare Lichtquellen kommen Germanium-basierte Leuchtdioden oder Laser auf Silizium-Substrat in Frage. Dafür ist eine intensive direkte Lumineszenz der Ge-Schicht nötig. Aus diesem Grund wurde der Einfluss von Donatorkonzentration, Verspannung, Quanten-Confinement und Versetzungsdichte auf die Lumineszenzintensität von Ge-Strukturen mittels Photo- und Elektrolumineszenz-Spektroskopie (PL bzw. EL) untersucht. Eine Antimon-Konzentration von 3e19/cm³ erhöhte die Intensität um das Vierfache im Vergleich zu einer intrinsischen Ge-Schicht. Eine zusätzliche Zugverspannung durch ein virtuelles Substrat aus GeSn erzielte nur eine geringfügige Intensitätssteigerung. Eine GeSn/Ge Multi-Quantum-Well (MQW) Struktur steigerte die Lumineszenz um den Faktor 16. Jedoch wurde durch transmissionselektronenmikroskopische Untersuchungen der Strukturen eine hohe Dichte von Durchstoßversetzungen (threading dislocations) im Bereich von 1e9/cm² gefunden. Diese bewirken eine Reduzierung der Lumineszenzintensität um zwei Größenordnungen, wie PL-Messungen an pseudomorph gewachsenen Ge/Si-MQW-Schichten zeigen. Eine Analyse der Strom-Spannungs-Kurven ergab einen weitaus weniger schädlichen Einfluss von Durchstoßversetzungen im Germanium als dies für Silizium der Fall ist. Im Hinblick auf eine Steigerung der direkten Ge-Lumineszenz sollten dotierte MQW-Strukturen und eine Reduzierung der Versetzungsdichte Anwendung finden.
Comparative STM-based study of thermal evolution of Co and Ni germanide nanostructures on Ge(001)
(2015)
Since 1947, when Bardeen and Brattain initiated the era of microelectronics by constructing the first Germanium (Ge) transistor, semiconductors have become the main material platform for advanced integrated circuit (IC) technologies. Later on, given in particular the electrical stability of its native oxide, IC technology shifted from Ge to Silicon (Si) substrates and the dominance of Si-based complementary metal oxide semiconductor (CMOS) microelectronics is today unquestionable. However, as the semiconductor industry is approaching the limits of traditional Si CMOS scaling, the integration of new materials into Si micro- and nano-electronics is required to extend the performance and functionality of future CMOS-based IC technologies.
Recently, Ge due to its superior optoelectronic properties and compatibility with conventional Si CMOS technology has re-emerged as an alternative semiconductor material on the mainstream Si technology platform. Many of the Ge integration challenges, such as e.g. doping, epitaxial quality etc., have been recently solved or minimized to an acceptable level. However, the fabrication of low resistance, thermally stable metal/Ge contacts is still one of the main barriers towards the full use of the potential offered by Ge. In particular, the formation of ohmic contacts is relevant for applications where high current densities are of importance (i.p. Ge p-MOSFET and Ge laser applications). Consequently, intensive investigations of metal/Ge contacts are imperative for future applications of Ge.
Various metal/Ge contact systems were studied and demonstrated good thermal stability and promising electrical properties. However, given their widespread use in Si CMOS technologies in form of their respective silicides, Co- and Ni-germanides seem to be an obvious choice for electrical contacts in Ge-based devices. Both metal/Ge systems exhibit a complex bulk phase diagrams with a wide range of different physical properties. It is generally acknowledged that the stoichiometric CoGe2 and NiGe phases are best suited for ohmic metal contact formation, mainly due to their low resistivity. It is worth noting that the bulk phase diagram is limited in its use for nanoscience due to an increased surface/volume ratio as well as by the strong nanostructure/substrate interface influence.
This PhD thesis sheds light on the formation process at the atomic level of Co and Ni germanide nanostructures on clean, reconstructed Ge(001) substrates. The main part of the presented research is based on in-situ scanning tunneling microscopy (STM) studies on the influence of subsequent, post-evaporation annealings at various temperatures in order to follow and investigate on the nano-scale the structural evolution of a few monolayers of Co and Ni metal (deposited at RT and in UHV conditions) on an atomically clean, reconstructed Ge(001) surface. Furthermore, additional techniques like LEED, (S)TEM-EDX and XPS were used to corroborate and complement the STM derived insights.
It was demonstrated that - for both investigated systems - room temperature deposition of a few metal monolayers on clean Ge(001) results in a Volmer Weber growth mode. Starting with annealing treatments at relatively low temperature ranges, the formation of a continuous MetalxGey wetting layer from as-deposited 3D metal clusters on Ge(001) was detected. It should be noted that a very flat wetting layer was observed for the Co/Ge(001) system, which is different for the Ni/Ge(001) system where inhomogeneous terraced domains were formed. Finally, the 2D wetting layer gradually evolves with increasing temperature into well-ordered 3D MetalxGey nanostructures, surrounded by clean, reconstructed Ge(001). Analysis of these Co and Ni germanide nanostructures shows that the growth mechanism is different: in particular the Ni/Ge system is more reactive by means of Ni bulk diffusion and results in 3D Ni germanide nanostructures which show a strong tendency to be embedded into the Ge(001) substrate. In contrast, Co germanide nanostructures are situated initially on top of the Ge(001) substrate due to the fact that Ge diffusion dominates in the low temperature range. Only at higher annealing temperatures, Co diffusion into the bulk occurs and Co germanide nanostructures penetrate into the Ge substrate. For the Co- as well as Ni-Germanide system, the nanostructures undergo Ostwald ripening phenomena in the high temperature range. The present PhD thesis thus allows to understand on the nano-scale the main growth and reaction mechanisms of the Walser and Benè rule set up about 40 years ago to describe metal/semiconductor interface reaction on the macro-scale.
Semiconductor nanowires, also called nanorods or nanowhiskers, are of particular interest for various applications in nanotechnology. Especially, germanium as a CMOS compatible material with its good electronic properties has gained renewed interest in recent years due to the availability of modern gate dielectrics. The present work deals with the vapor-liquid-solid growth of germanium nanowires and their characterization. The Growth has been carried out by means of molecular beam epitaxy using differently oriented germanium and silicon substrates whereas gold has been used to create metal catalyst droplets with radii of typically 100 nm and below. All stages from the substrate preparation to the final growth have been investigated in the frame of this work to find significant control parameters that influence the growth result. The droplet formation by means of gold evaporation onto the heated substrates has been investigated extensively on different substrates and for different surface preparations to identify parameters that are crucial for the resulting size distribution. Thereby sticking effects of the droplet circumference turned out to influence the radius distribution significantly. Germanium nanowires have been observed to grow preferentially along the <011> crystallographic directions on all utilized substrate orientations leading to defined possible inclinations of the wires with respect to the substrate normal. In contrast to the faceting known from silicon wires, the sidewalls mainly exhibit four flat {111} facets whereas the tip is roof shaped consisting of another two {111} facets. Different models which describe the inclined growth are presented and discussed. Furthermore, the material transport during the growth has been investigated. The nanowire length was found to be up to eight times larger than the nominal layer thickness according to the total amount of deposited germanium which is explained by surface diffusion towards the nanowires. The diffusion dominated growth regime was confirmed by length-radius-plot showing a decrease of the nanowire length at increasing radii. A temperature dependent diffusion model has been utilized to describe the observed nanowire length as a function of the substrate temperature. Beside conventional nanowires, so-called in-plane nanowires which grow along the substrate surface have been studied. Like their vertically growing counterparts, they also tend to grow along <011> in-plane directions which is particularly distinct on Ge(011) substrates. However, the fraction of nanowires which are aligned along <011> is influenced by substrate imperfections which was intentionally affected by means of wet-chemical substrate preparation. In addition to the nanowire growth, techniques for selective catalyst removal as well as for nanowire embedding in an insulating, transparent matrix have been established which can be important prerequisites for further nanowire processing in terms of electric or optoelectronic applications.
On the compliant behaviour of free-standing Si nanostructures on Si(001) for Ge nanoheteroepitaxy
(2012)
Due to its superior optoelectronic properties, Germanium (Ge) is attracting increasing interest to build up future photonic modules within Si chip baseline technology. Despite clear advantages of Ge integration in Si technology (identical diamond crystal structure with Si, complementary metal oxide semiconductor (CMOS) compatibility due to no contamination risks etc.), it faces also some true challenges limiting the optoelectronic performance. Among them, thermal and lattice mismatch result in too high defect levels (which act as non-radiative recombination centres). Parasitic diffusion and formation of SiGe alloys at elevated temperatures is also a common problem. In this respect, selective chemical vapor deposition Ge heteroepitaxy approaches for high quality Ge nanostructure growth with reasonable thermal budget must be developed for local Ge photonic module integration. A promising vision is offered by the compliant substrate effects within nanometer scale Ge/Si heteroepitaxial structures. Here, in contrast to the classical Ge deposition on bulk Si substrates, the thermal and lattice mismatch strain energy accumulated in the Ge epilayer is partially shifted to the free-standing Si nanostructure. This strain partitioning phenomenon is at the very heart of the nanoheteroepitaxy theory (NHE) and, if strain energy levels are correctly balanced, offers the vision to grow defect-free nanostructures of lattice mismatched semiconductors on Si. In case of the Ge/Si heterosystem with a lattice mismatch of 4.2%, the strain partitioning phenomenon is expected to be triggered when free-standing Si nanopillars with the width of 50 nm and below are used. In order to experimentally verify NHE with its compliant substrate effects, a set of free-standing Ge/Si nanostructures with diameter ranging from 150 to 50 nm were fabricated and investigated. The experimental verification of compliant substrate effects is challenging and requires sophisticated characterization techniques. The main limitation corresponds to a simultaneous detection of a) the strain partitioning phenomenon between Ge and Si and b) the absence of defects on the nano-scale. In this respect, synchrotron-based grazing incidence x-ray diffraction was applied to study the epitaxial relationship, defect and strain characteristics with high resolution and sensitivity in a non-destructive way. Raman spectroscopy supported by finite element method calculations were used to investigate the strain distribution within a single Ge/Si nanostructure. Special focus was devoted to transmission electron microscopy to determine the quality of the Ge epilayer. It was found, that although high quality Ge nanoclusters can be achieved by thermal annealing on Si pillars bigger than 50 nm in width, no proof of strain partitioning phenomenon was observed. In clear contradiction to the present NHE theory, no strain partitioning phenomenon was found even for ~50 nm wide Si pillars for which the compliant substrate effects are expected. The absence of the strain partitioning between Ge and Si is caused by the stress field exerted by the SiO2 growth mask on the Si nanopillar. In contrast to such nanostructures monolithically prepared from a Si(001) wafer, first results in this thesis clearly prove the strain partitioning phenomenon within Ge/Si nanostructures on Silicon–on–insulator substrate. Here, the compliant substrate effects were clearly observed for pillar widths even bigger than 50 nm. This experimental work demonstrates, that NHE with its compliant substrate effects, offers an interesting approach for high quality Ge nanostructures on Si, avoiding even the misfit dislocation network with its non-tolerable electrical activity in Ge nanodevices. However, the theory does not yet include important aspects of thin film growth on the nano-scale and must be further developed. It is the aim of this PhD thesis to provide this experimental basis for the Ge/Si heterosystem. Finally, it is noted that here developed growth approach is fully Si CMOS compatible and is not only relevant for Ge integration but also for other lattice mismatched alternative semiconductors (GaAs etc.) to enable higher performance / new functions in future Si microelectronics technologies.
During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.
In der Arbeit wird untersucht, inwieweit zwei Epitaxieverfahren (LPCVD- und RPCVDVerfahren) geeignet sind, Bor-dotierte Si/SiGe/Si-Heteroschichtstapel mit guter Homogenität und Reproduzierbarkeit herzustellen. Die Bewertung der Epitaxieverfahren erfolgte anhand von HBT-Parametern, deren Streuungen von Wafer zu Wafer und über den Wafer ermittelt und mit publizierten Referenzdaten des etablierten UHVCVD-Verfahrens verglichen wurden. Die besten Ergebnisse wurden für RPCVD-basierte Si/SiGe/Si-Schichstapel ermittelt. Schichtstapel beider Epitaxieverfahren haben eine geringe Dichte elektrisch aktiver Defekte. Als kritischer Epitaxieprozeßparameter wurde die Abscheidetemperatur ermittelt. Im Fall des LPCVD-Verfahrens hat die Trägergasgeschwindigkeit einen großen Einfluß auf die Homogenität des Boreinbaus. Mit dieser Arbeit wurde nachgewiesen, daß das RPCVDEpitaxieverfahren eine Alternative zum etablierten UHVCVD-Verfahren ist.
Diese Arbeit besteht aus zwei Teilen. Der erste Teil zeigt eine Untersuchung mechanischer Verspannungen in Silizium Bauelementestrukturen, die mit Variationen des "shallow trench isolation" (STI) Prozesses hergestellt wurden. Die Messungen wurden mit hoher Ortsauflösung mittels Mikro-Raman Spektroskopie durchgeführt. Zur Anregung wurde ultraviolettes (364 nm) Laserlicht verwendet. Die Arbeit beschreibt detailiert die Vorteile von UV gegenüber sichtbarem Licht und diskutiert den Einfluss verschiedener Prozessparameter auf die mechanische Verspannung im Si Substrat. Eine Korrelation zwischen mechanischer Verspannung und Defektbildung sowie degradierender elektrischer Eigenschaften wird gezeigt. Der zweite Teil dieser Arbeit präsentiert die Untersuchung der Phononen in SiGe Volumenkristallen. Die Messungen mittels Raman Spektroskopie leisten einen Beitrag zur Klärung widersprüchlicher Moden-Zuordnungen. Das Verhalten des Ge-Phonons unter Beimischung von Si in einen reinen Ge-Kristall wird gezeigt. Die Zuordnung der lokalisierten Si-Schwingungsmode (Si LVM) konnte experimentell durch die Beobachtung der Schwingungen aller drei Si Isotope bestätigt werden.