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Mixed signal integrated circuits (MSICs) contain both analog and digital circuitry, integrated together on the same die. While this integration brings many benefits, it also gives rise to the issue of substrate noise coupling between the noisy digital circuitry and noise-sensitive analog circuitry. In order to counteract this issue, various substrate noise reduction methodologies had been developed so far. This thesis explores a new approach in substrate noise reduction – using a GALS (globally-synchronous, locally-asynchronous) design strategy for the digital part of a MSIC, in order to reduce the noise generation at its source. GALS architectures consist of several locally synchronous modules (LSMs) which communicate asynchronously to each other. By converting an initially synchronous architecture of digital circuitry into a GALS architecture, simultaneous switching noise generated by this circuitry can be reduced. While GALS had already been used for reducing other types of simultaneous switching noise, this is, to the best of the author’s knowledge, the first attempt to develop a GALS-based methodology for substrate noise reduction. In order to be able to theoretically analyze GALS-based methodologies for substrate noise suppression, corresponding models at high abstraction level for substrate noise generation and substrate noise propagation in lightly doped substrates (which is a type of substrate mostly used for MSICs) have been developed. These models have further been used for developing two new GALS-based substrate noise reduction methodologies: harmonic-balanced plesiochronous GALS partitioning (HB) and harmonic-and-area-based plesiochronous GALS partitioning with power domain separation (HAB). A theoretical analysis has shown that HB can reach substrate noise attenuation of up to 20log(M), where M is the number of LSMs of the resulting GALS system. On the other hand, the attenuation achievable by HAB depends on the distribution of switching current harmonics and area among the partitions, as well as from the substrate itself. For each of the two methodologies, a suitable partitioning procedure for a practical application has been developed; these partitionig procedures have been numerically evaluated in MATLAB. HB has further been embedded within the EMIAS CAD tool, where it has been evaluated on a real design example – a wireless sensor node. A special case of HAB for low frequencies has been applied for developing a test chip called SGE (power domain Separation and Galsification Experiment). The measurements on silicon have proved the applicability of the methodology.
In this thesis a novel Globally Asynchronous Locally Synchronous (GALS) technique applicable to wireless communication systems and generally to datapath architectures is presented. The proposed concept is intended for point-to-point communication with very intensive but bursty data transfer. This concept is based on a request-driven operation of locally synchronous modules. The key idea is that a module can use the input request signal as its clock while receiving a burst of data. The developed GALS technique is applied to the design of an IEEE 802.11a compliant baseband processor with the aim to alleviate the problems of system integration, power consumption and electro-magnetic interference. The GALS design was compared with a synchronous version of the baseband processor. In our experimental setup we have measured a 1% reduction in dynamic power consumption, 30% reduction in instantaneous supply voltage variations, and 5 dB reduction in spectral noise.