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In this work a compact, monolithically integrated, high frequency sigma-delta phase-locked loops (PLLs) designed in 0.13 μm CMOS technology are investigated. The research focuses on the analysis of PLL spurious performance degradation caused by the integrated digital sigma-delta modulator, design and optimization of compact sigma-delta modulators with improved tonal and switching noise performance. The main achievements of this work include: 1. An implementation of MASH (multistage) modulator in the dual edge triggered style is proposed. The implementation offers two advantages over conventional MASH when integrated into the same die with a fractional-N PLL: 1) the modulator’s area is reduced by 15–20%; 2) the switching noise power is distributed in such a manner, that the first reference spur of a synthesizer is not degraded; instead, the glitch energy is shifted to the second multiple of reference frequency; in the work a benefit of such reference spur power distribution is demonstrated. Proposed implementation does not affect logical behavior of the MASH modulator. 2. MASH 1-1-1 (three stages of first order each) sigma-delta modulator with DC dithering used for frequency synthesis applications is investigated. At the expense of minimum additional hardware such dithering topology allows to shift tones to the low frequencies and decrease their power. 3. An oscillator-based dither generator is proposed for the use in MASH 1-1-1 modulator. The generator consumes less current and area, produces much less supply switching noise than a conventional pseudo-random dither generator while keeping modulator’s output free of tones. An empirical study of oscillator-based dither generator is presented. 4. MASH 1-1-1 modulator with direct feedback dithering is investigated. Such dithering topology requires no additional hardware to be implemented. Among the disadvantages of the direct feedback dithering is the addition of small DC offset to the output of MASH modulator and presence of some low power tones in amplitude spectrum. Two fully integrated 11 GHz sigma-delta PLLs incorporating single- and dual edge triggered MASH modulators with different dithering topologies were fabricated in 0.13 μm CMOS process. Spurious, as well as phase noise performance of the PLLs for different modulator topologies was compared. The PLL controlled by the integrated dual edge triggered MASH 1-1-1 modulator exhibited first reference spur below –66 dBc over the whole locking range and fractional spurs power not exceeding –70 dBc within 70% of the division ratio range.
Ziel dieser Arbeit ist die Vorstellung und Diskussion einer neuartigen Schaltungstechnik für Dual-Modulus Hochfrequenzvorteiler mit einem niedrigen Leistungsverbrauch. Diese neue Schaltungstechnik wird verifiziert im System einer Phasenregelschleife. Diese PLL ist das zentrale Element in Sender- und Empfängerschaltungen. In Frequenzsynthesizern der Mobilkommunikation werden bis zu 90% der Gesamtverlustleistung vom Dual-Modulus HF Vorteiler beansprucht. Mit Hilfe der in dieser Arbeit vorgestellten Schaltungstechnik kann annähernd das gleiche Produkt aus Geschwindigkeit und Verlustleistung für den HF Vorteiler erreicht werden, wie in einfachen Binärteilern. Grenzen einfacher CMOS Schaltungen werden verglichen mit denen der CML Schaltungstechnik.