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Conventional semiconductor memories are facing many challenges concerning their yield, reliability, testability, and manufacturability as the feature size decreases. Although they are used in the vast majority of electronic devices, their applicability for upcoming digital systems is questionable. On the other hand, due to unprecedented development of mobile devices even faster, denser, and more power-efficient semiconductor memories are required. As a consequence, many researchers and system designers are seeking new memory solutions. The greatest attention is paid to solid-state, non-volatile memories (NVMs) such as PCRAMs, MRAMs/STT-MRAMs, FeRAMs, and RRAMs. Due to their promising features like non-volatility, low-power consumption, and great scalability they are expected to meet the challenging demands of future digital systems.
Unfortunately, despite all advantages they offer, emerging NVMs pose some peculiar characteristics like limited endurance, variable data retention time, or vulnerability to external factors. On top of that, they are still in early-maturity state where their fabrication processes are not of high quality and are prone to high variations. Because of that, emerging NVMs may suffer from permanent faults which can occur right after production or in the field, during their operational time. As a consequence, the reliability of new memory technologies requires special management and great improvement.
The thesis introduces system-level approach aimed at comprehensive reliability management of existing and emerging NVMs. It presents novel on-line repair techniques which focus on specific issues of NVMs. The block-level repair manages post-production faults in the memory array. The word-level repair aims at hard faults caused by wear-out memory cells. Finally, the error-correcting code with increased hard-error correction capability handles soft and hard errors in the memory array.
Because proposed techniques are based on similar principles, they can be combined into a consistent system. Depending on the way how they are connected, different repair schemes can be achieved. Moreover, by merging them into the system a synergistic effect can be produced where the achieved memory reliability improvement is greater than the sum of reliability improvements achieved with their standalone implementations.
Further in the thesis, such a consistent repair system is presented. Next, its effectiveness, repair capabilities, and applicability for an embedded system are evaluated. In addition, the achieved synergistic effect is described and quantified
The reliability of interconnects on integrated circuits (IC) has become a major problem in recent years because of the rise of complexity, the low-k-insulating material with reduced stability, and wear-out-effects from high current densities. The total reliability of a system on a chip is increasingly influenced by the reliability of the interconnections, which is caused by increased communication from the elevated number of integrated functional units. In recent years, studies have predicted that static faults will occur more often decreasing the reliability and the mean time to failure. The most published solutions aim to prevent dynamic faults and to correct transient faults. However, built-in self-repair (BISR) as a solution for static faults has not previously been discussed along with the other possible solutions. Theoretically, BISR can lead to higher reliability and lifetime. This is my motivation to implement BISR for integrated interconnects. Because BISR cannot repair transient and dynamic faults, I combine BISR with other approved solutions in this thesis. The results show that the combination leads to higher reliability and lifetime with less area and static power overhead compared to the existing solutions.