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Effects of advanced process approaches on electromigration degradation of Cu on-chip interconnects
(2007)
This thesis provides a methodology for the investigation of electromigration (EM) in Cu-based interconnects. An experimental framework based on in-situ scanning electron microscopy (SEM) investigations was developed for that purpose. It is capable to visualize the EM-induced void formation and evolution in multi-level test structures in real time. Different types of interconnects were investigated. Furthermore, stressed and unstressed samples were studied applying advanced physical analysis techniques in order to obtain additional information about the microstructure of the interconnects as well as interfaces and grain boundaries. These data were correlated to the observed degradation phenomena. Correlations of the experimental results to recently established theoretical models were highlighted. Three types of Cu-based interconnects were studied. Pure Cu interconnects were compared to Al-alloyed (CuAl) and CoWP-coated interconnects. The latter two represent potential approaches that address EM-related reliability concerns. It was found that in such interconnects the dominant diffusion path is no longer the Cu/capping layer interface for interconnects as in pure Cu interconnects. Instead, void nucleation occurs at the bottom Cu/barrier interface with significant effects from grain boundaries. Moreover, the in-situ investigations revealed that the initial void nucleation does not occur at the cathode end of the lines but several micrometers away from it. The mean times-to-failure of CuAl and CoWP-coated interconnects were increased by at least one order of magnitude compared to Cu interconnects. The improvements were attributed to the presence of foreign metal atoms at the Cu/capping layer interface. Post-mortem EBSD investigations were used to reveal the microstructure of the tested samples. The data were correlated to the in-situ observations.