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Due to the unique electronic band structure, graphene has opened the great potential to extend the functionality of a large variety of graphene-based devices in health and environment, energy storage, or various microelectronic applications, to mention a few. At this point, the implementation of graphene into Silicon (Si) semiconductor technology is strongly dependent on several key challenges. Among them, high-quality and wafer-scale graphene synthesis on CMOS compatible substrates is of the highest importance. Though large-area graphene can be achieved on substrates like copper, platinum, silicon carbide, or single-crystal Ni, however, high growth temperatures, unavailability of large scale, or contamination issues are the main drawbacks of their usage. In this PhD work, 8-inch scale graphene synthesis is attempted on alternative substrates such as epitaxial Germanium on Si and polycrystalline Nickel on Si. To achieve the growth of the highest quality of graphene, this work focuses on the investigations of various nucleation and growth mechanisms, substrate–graphene interfaces, effects of different substrate orientations, and detailed microscopic and macroscopic characterization of the grown films. Finally, it should also be stressed that the experiments in this work were carried out in a standard BiCMOS pilot-line, making this study unique, as its results might directly pave the way to further graphene integration and graphene-based device prototyping in mainstream Si technologies.
In der Arbeit wird untersucht, inwieweit zwei Epitaxieverfahren (LPCVD- und RPCVDVerfahren) geeignet sind, Bor-dotierte Si/SiGe/Si-Heteroschichtstapel mit guter Homogenität und Reproduzierbarkeit herzustellen. Die Bewertung der Epitaxieverfahren erfolgte anhand von HBT-Parametern, deren Streuungen von Wafer zu Wafer und über den Wafer ermittelt und mit publizierten Referenzdaten des etablierten UHVCVD-Verfahrens verglichen wurden. Die besten Ergebnisse wurden für RPCVD-basierte Si/SiGe/Si-Schichstapel ermittelt. Schichtstapel beider Epitaxieverfahren haben eine geringe Dichte elektrisch aktiver Defekte. Als kritischer Epitaxieprozeßparameter wurde die Abscheidetemperatur ermittelt. Im Fall des LPCVD-Verfahrens hat die Trägergasgeschwindigkeit einen großen Einfluß auf die Homogenität des Boreinbaus. Mit dieser Arbeit wurde nachgewiesen, daß das RPCVDEpitaxieverfahren eine Alternative zum etablierten UHVCVD-Verfahren ist.
In this work, growth and characterisation of 3C-SiC thin films, investigation of oxidation of thus prepared layers and Pr-silicate and AlON based interface with SiC have been studied. Chemical vapor deposition of 3C-SiC thin films on Si(001) and Si(111) substrates has been investigated. Prior to the actual SiC growth, preparation of initial buffer layers of SiC was done. Using such a buffer layer, epitaxial growth of 3C-SiC has been achieved on Si(111) and Si(001) substrates. The temperature of 1100°C and 1150°C has been determined to be the optimal temperature for 3C-SiC growth on Si (111) and Si(001) substrates respectively. The oxidation studies on SiC revealed that a slow oxidation process at moderate temperatures in steps was useful in reducing and suppressing the g-C at the SiO2/SiC interface. Clean, graphitefree SiO2 has been successfully grown on 3C-SiC by silicon evaporation and UHV anneal. For the application of high-k Pr2O3 on silicon carbide, plausible interlayer, Pr-Silicate and AlON, have been investigated. Praseodymium silicate has been prepared successfully completely consuming the SiO2 and simultaneously suppressing the graphitic carbon formation. A comparatively more stable interlayer using AlON has been achieved. This interlayer mainly consists of stable phases of AlN along with some amount of Pr-aluminates and CN. Such layers act as a reaction barrier between Pr2O3 and SiC, and simultaneously provide higher band offsets.