Refine
Document Type
- Doctoral thesis (4)
- Report (1)
Has Fulltext
- yes (5)
Is part of the Bibliography
- no (5)
Keywords
- CMOS-Schaltung (5) (remove)
With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors.
Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail.
In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.
Mathematically, cryptographic approaches are secure. This means that the time an attacker needs for finding the secret by brute forcing these approaches is about the time of the existence of our world. Practically, an algorithm implemented in hardware is a device that generates a lot of additional data during calculation. Its power consumption, electromagnetic radiation etc. can be measured, saved and analysed for the key extraction. Such attacks - the side channel analysis attacks (SCA attacks) - are significant threats when applying cryptographic algorithms. By taking the issue of physical attacks into consideration when implementing a cryptographic algorithm, it is possible to design an implementation that is resilient - at least to a certain extend - against side channel analyses. In this report, we give implementation details of the IHP accelerator for the elliptic curve point multiplication. We analysed the implemented algorithm ow and its power consumption using simulated power traces for the 130nm CMOS IHP technology. We made a horizontal power analysis attack using the difference-of-means test with the goal of finding potential SCA leakage sources, i.e. finding the operations in the algorithmic ow that are responsible for the correct extraction of the cryptographic key.
Die vorliegende Arbeit befaßt sich mit der Entwicklung von MOS-Transistoren mit lateral erweitertem Drainanschluss (LDMOS) und deren Integration in eine 0.13µm SiGe:C-BiCMOS-Technologie. In dieser Technologie stehen neben SiGe-Heterobipolartransistoren (HBT) auch komplementäre MOS Feldeffekttransistoren (MOSFET) für Betriebsspannungen von 1.2V und 3.3V sowie passive Bauelemente, wie z.B. integrierte Kondensatoren, Widerstände und Spulen, zur Verfügung. Die 0.13µm-BiCMOS-Technologie verbindet so die Vorteile eines skalierten CMOS-Prozesses, z.B. für Digitalschaltungen mit hohen Rechenleistungen, mit den sehr guten Hochfrequenzeigenschaften der SiGe-HBTs. Damit ermöglicht sie neuartige Anwendungen im Millimeterwellenbereich, wie z.B. in optischen Netzwerken mit Übertragungsraten über 100 Gb/s oder in drahtlosen Kommunikationssystemen. Die zusätzliche Integration von Hochvolt-MOSFETs, mit der sich diese Arbeit befasst, ermöglicht eine erweiterte Funktionalität der mittels der BiCMOS-Technologie herstellbaren Schaltkreise. In der Regel verlangt die Herstellung von Hochvolttransistoren in etablierten BiCMOS- oder CMOS-Umgebungen meist zusätzlichen Prozessaufwand zu den Standardabläufen. Ein wesentliches Ziel dieser Arbeit war die Entwicklung von Integrationskonzepten die diesen technologischen Mehraufwand minimieren. Im ersten Teil dieser Arbeit wird ein Integrationskonzept entwickelt, welches die Herstellung komplementärer LDMOS-Transistoren erlaubt, d.h. LDMOS-Transistoren mit n-Kanal (NLDMOS) als auch p-Kanal (PLDMOS), und einen zusätzlichen Maskenschritt pro Transistortyp im Vergleich zum Basisprozess erfordert. Dabei wird speziell die Driftregion des NLDMOS-Transistors und insbesondere der Einfluss eines innerhalb der n-dotierten Driftregion realisierten p-dotierten Gebietes untersucht. Im zweiten Teil dieser Arbeit wird ein neuartiges Prinzip zur Realisierung von Hochvolttransistoren ohne zusätzlichen Prozessaufwand vorgestellt. Dabei wird die schwach dotierte Driftregion durch eine spezielle Kombination von Implantationen des Basis-CMOS-Prozesses hergestellt. Das vorgestellte Konzept wird so optimiert, dass es auch die Realisierung von komplementären Hochvolttransistoren erlaubt. Trotz des minimalen bzw. keines technologischen Mehraufwandes bei der Realisierung der komplementären Transistoren erzielen die Bauelemente Spitzenwerte in den Grenzfrequenzen bei den entsprechenden maximalen Betriebs- und Durchbruchspannungen für Si-basierte LDMOS-Transistoren.
In this work a compact, monolithically integrated, high frequency sigma-delta phase-locked loops (PLLs) designed in 0.13 μm CMOS technology are investigated. The research focuses on the analysis of PLL spurious performance degradation caused by the integrated digital sigma-delta modulator, design and optimization of compact sigma-delta modulators with improved tonal and switching noise performance. The main achievements of this work include: 1. An implementation of MASH (multistage) modulator in the dual edge triggered style is proposed. The implementation offers two advantages over conventional MASH when integrated into the same die with a fractional-N PLL: 1) the modulator’s area is reduced by 15–20%; 2) the switching noise power is distributed in such a manner, that the first reference spur of a synthesizer is not degraded; instead, the glitch energy is shifted to the second multiple of reference frequency; in the work a benefit of such reference spur power distribution is demonstrated. Proposed implementation does not affect logical behavior of the MASH modulator. 2. MASH 1-1-1 (three stages of first order each) sigma-delta modulator with DC dithering used for frequency synthesis applications is investigated. At the expense of minimum additional hardware such dithering topology allows to shift tones to the low frequencies and decrease their power. 3. An oscillator-based dither generator is proposed for the use in MASH 1-1-1 modulator. The generator consumes less current and area, produces much less supply switching noise than a conventional pseudo-random dither generator while keeping modulator’s output free of tones. An empirical study of oscillator-based dither generator is presented. 4. MASH 1-1-1 modulator with direct feedback dithering is investigated. Such dithering topology requires no additional hardware to be implemented. Among the disadvantages of the direct feedback dithering is the addition of small DC offset to the output of MASH modulator and presence of some low power tones in amplitude spectrum. Two fully integrated 11 GHz sigma-delta PLLs incorporating single- and dual edge triggered MASH modulators with different dithering topologies were fabricated in 0.13 μm CMOS process. Spurious, as well as phase noise performance of the PLLs for different modulator topologies was compared. The PLL controlled by the integrated dual edge triggered MASH 1-1-1 modulator exhibited first reference spur below –66 dBc over the whole locking range and fractional spurs power not exceeding –70 dBc within 70% of the division ratio range.
This work demonstrates the design and implementation of a multi-band multi-standard WLAN system consisting of a 5 - 6 GHz receiver and a 24 GHz down-converter. The main challenges are high frequency, broadband, and adaptive operation, power consumption and high integration level. This thesis introduces a multi-standard adaptive receiver concept to fulfill those requirements. The receivers are implemented in a standard 0.13 µm CMOS technology. A direct-conversion architecture for the 5 - 6 GHz band and a heterodyne architecture for a multi-band system are proposed. The most common receiver architectures are analyzed and the wave propagation effects are discussed. Then the most important receiver parameters are derived. Active and passive integrated components are investigated because understanding the device characteristic is a key requirement for a successful high frequency design. Finally, the multi-standard adaptive receiver concept is introduced. The choice of architecture, design and implementation of each of the receiver building blocks are discussed. The functionality of the 5 - 6 GHz receiver and the 24 GHz down-converter is demonstrated by the performance measurements. The main achievements of this work include: Firstly, a 5-6 GHz LNA integrated in 0.13 µm CMOS technology. The amplifier exhibits a gain of 16.5 dB, noise figure of 2.9 dB and 1 dB input compression point of -6.5dBm at power consumption of 7.5mW. The circuit features robust built-in input ESD protection. Secondly, a 5-6 GHz zero-IF receiver with analog pre-processing features a noise figure of 3.8 dB at the conversion gain of 43.4 dB. The channel select filter corner frequency is tunable to 6.5, 10, 20 and 50 MHz. The implemented analog pre-processing loop allows to adopt the linearity of the receiver to the input signal level. Thirdly, a 23-24 GHz tuned down-converter achieved the gain of 21.8 dB, noise figure of 6.8 dB and 1 dB input compression point of -16.7dBm at power consumption of 58.5mW.