Refine
Document Type
- Doctoral thesis (6)
Has Fulltext
- yes (6)
Is part of the Bibliography
- no (6)
Keywords
- CMOS (6) (remove)
Energy efficiency is vital for future low-power electronic applications. This ultra-low power consumption requirement enables the research beyond the conventional charge-based memories. Further, reliability, high scalability, fast switching, CMOS compatibility, high endurance, etc., are some of the characteristics envisaged by the new generation of emerging non-volatile memories (NVMs). A memristor or OxRAM is one among the many emerging NVMs, which can exhibit the aforementioned characteristics, and it has the potential to replace the power-hungry conventional NVMs.
The memristive devices have the advantage of monolithic integration with the CMOS logic, which enables the widening of their application areas. Despite their various advantages, the reliability, forming voltages, and variability of the devices pose a hurdle to their wide commercial usage. Hence, it is crucial to identify these factors and mitigate them. This thesis addresses these issues through fabrication process improvements, electrical characterization techniques, and device-engineering methods.
The improvements in the fabrication processes reduced the pristine state currents of the memristive devices. It impacted the reliability and resistive switching performance of the memristive devices directly. To further improve the performance, the memristive devices are integrated into the 130 nm BiCMOS baseline technology of IHP. Additionally, dedicated test structures are developed to monitor and control the fabrication process steps through in-line electrical characterization.
Further, the forming current and voltage values, along with their dispersions in the 4 kbit memristive arrays, were reduced by utilizing the electrical characterization techniques. Accordingly, the forming operations were performed at high operating temperatures using incremental step pulse and verify algorithm (ISPVA). In contrast to the well-known method of increasing the current compliance (1R) or the gate voltage of the transistor (1T-1R) to increase the conduction filament size, a thin layer of Al2O3 is added. This device engineering technique reduced the variability in both LRS and HRS currents of the memristive devices. Additionally, the conduction filament properties in both states are modeled by using the quantum point contact (QPC) model. Finally, harnessing the intrinsic variability of the memristive devices for neuromorphic computing applications is demonstrated. The reliability of the devices is assessed through endurance and retention characteristics.
The rapid detection of infectious diseases is still an unsolved problem since their identification must be carried out either by cultivation or DNA analysis in a laboratory. The development of point-of-care (PoC) is a current development trend that requires further technological impulses to produce reliable and cost-effective systems. By miniaturizing and integrating microfluidic and electronic components, the advantages of electronic methods can be transferred to the field of PoC testing. The combination of complementary metal-oxide-semiconductor (CMOS) technology with microfluidic platforms allowed the development of fully functional sample-to-result LoC setups, which served the portability of the device even out of the laboratory or hospitals. CMOS-based LoC device can control and manage the data from sensors, microfluidics, and actuators. Dielectrophoresis (DEP) is a non-destructive and non-invasive method promising to be used in PoC medical applications. Utilizing MEMS technology and fabrication of microelectrodes allow DEP to be applied in biomedical applications such as cell manipulation and separation with high speed, sensitivity and without any labeling. Cell detection and separation occupy an important place in diagnostics of viral and infectious diseases such as Influenza and COVID-19. Therefore, rapid, sensitive, and automated LoC devices are needed to detect such diseases. Starting from this point of view, manipulating the cells as a way to detect them using DEP was decided as the main objective of the thesis.
This work aimed at developing a miniaturized CMOS integrated silicon microfluidic device, in line with a standard CMOS procedure, for characterization and manipulation of live and dead yeast cells using the DEP technique. Understanding the relationship between the microelectrode’s geometry and the magnitude of DEP force, the microfluidic devices can be designed to produce the most effective DEP implication on biological samples. In this work, interdigitated electrode arrays (IDEs) were used to manipulate the cells. This microelectrode was primarily used to detect microorganisms in a solution, based on the measurement of the variation of the dielectric constant by the concentration of the microorganisms. Therefore, finite element simulations were performed to optimize this microelectrode and adapt it to our application. Thus, the IDEs were optimized as a function of finger width and spacing between adjacent fingers. One of the most serious matters related to DEP-based microfluidic devices is that the DEP spectra of the targeted cell should precisely be known. Therefore, the DEP spectrum analysis of various cell suspensions with different medium conductivities was studied comprehensively by finite element simulation and experimentally. This study presented an optimized trapping platform for both detection and separation applications in terms of electrode dimension and electrical parameters.
Einleitung: Akustische Oberflächenwellenfilter (SAW Filter) finden in zahlreichen drahtlosen und drahtgebundenen Kommunikationstechnologien sowie in der Sensorik ihren Einsatz. Dabei führt der Trend hin zu immer preiswerteren und kompakteren Lösungen mit noch mehr Funktionalität und noch geringeren Stromverbräuchen. Die Anwendungen erstrecken sich dabei von ultraenergiesparenden Kommunikationssystemen (z. B. für Sensorknoten) bis hin zu preiswerteren Multisensorarrays in der Sensorik (z. B. Biosensoren) sowie auf einem Chip integrierten Mikrofluidik Systemen (z. B. Mikroliterpumpen). Eine Lösung stellt die Integration der SAW Filter auf einem Chip zusammen mit integrierten Schaltkreisen (IC) in der sogenannten komplementären-Metall-Oxid-Halbleiter (CMOS) Technologie dar. Da es sich hierbei um ein neues Forschungsgebiet handelt und nur wenige Forschergruppen auf diesem Gebiet arbeiten sind umfangreiche wissenschaftliche Untersuchungen notwendig, um eine vollständige Integration der SAW Filter zu ermöglichen. Das einzige reinraumkompatible piezoelektrische Material mit einem ausreichend hohen elektromechanischen Kopplungsfaktor (K2) sowie einer hohen akustischen Ausbreitungsgeschwindigkeit (vAlN = 5760 m/s [Bu 2006]) für hohe Arbeitsfrequenzen (bis ~6 GHz) ist dabei Aluminiumnitrid (AlN). Dafür muss es hoch c-achsenorientiert (<2°) aufgewachsen werden. Ein großes Problem bei der Integration ist das elektromagnetische Übersprechen (Crosstalk), welches besonders auf den für die CMOS Technologie notwendigen niederohmigen Siliziumsubstraten auftritt.
Ziel: Diese Doktorarbeit untersucht die Möglichkeit der Integration von AlN basierten SAW Filtern mit Hilfe von diskreten Bauelementen, aufgebaut mit CMOS kompatiblen Schichtsystemen, in Hinblick auf eine spätere CMOS kompatible Vollintegration.
Ergebnisse: Es konnte gezeigt werden, dass AlN basierte Filter mit Hilfe von CMOS kompatiblen Materialien und Prozessschritten hergestellt werden können. Außerdem konnte gezeigt werde, dass AlN sehr gut (full width at half maximum, FWHM: 1,27° - 1,9°) c-achsenorientiert aufgewachsen werden kann. Umfangreiche Simulationen, die mit Hilfe der finiten Element Methode (FEM) durchgeführt wurden, zeigten akustische Wellen (Rayleighwelle R0 und an der Oberfläche geführte Volumenwelle R1) mit Geschwindigkeiten von circa 4200 m/s (R0) bzw. 5200 m/s (R1) im technisch relevanten Frequenzbereich (~2,4GHz). Es wurde festgestellt, dass die akustische Reflektivität von Wolfram basierten Fingerelektroden circa ein bis zwei Größenordnungen höher liegt als bei Aluminium basierten Elektroden. Hergestellte SAW Filter zeigten maximale Resonanzfrequenzen von 3,3 GHz bei einer Wellenlänge von 1,68 µm, diese können noch auf bis zu 6,6 GHz bei einer minimalen Wellenlänge von 0,8 µm gesteigert werden. In dieser Arbeit konnte erstmals ein elektromagnetisches Übersprechen (Crosstalk) von unter -65 dB auf standardmäßig niederohmigen Siliziumsubstraten gezeigt werden. Erste optimierte SAW Filteranwendungen zeigten typische Frequenzantworten mit guter Performance.
This work addressed the challenges of accurate mm-wave characterization of devices fabricated in advanced semiconductor technologies. It developed the in-situ calibration solution that is easy to be implemented for silicon technologies. The new technique was verified up to 110 GHz on three difference processes: high performance SiGe:C BiCMOS from IHP Microelectronics (Germany), BiCMOS9MMW from STMicroelectronics (France), and RF CMOS 8SF from IBM Microelectronics (USA). The measurement frequency was solely limited by the capability of the test equipment. Practical results demonstrated that proposed in-situ calibration significantly outperforms the convention method independently on the process specifics and complexity. Some important aspects of the on-wafer S-parameter measurement assurance were presented as well. The discussion included the analysis of the calibration residual errors caused by the improper boundary conditions of coplanar calibration standards and the impact of the RF probe tip design. In conclusion, some suggestions for further accuracy improvement of the proposed method are given.
This work demonstrates the design and implementation of a multi-band multi-standard WLAN system consisting of a 5 - 6 GHz receiver and a 24 GHz down-converter. The main challenges are high frequency, broadband, and adaptive operation, power consumption and high integration level. This thesis introduces a multi-standard adaptive receiver concept to fulfill those requirements. The receivers are implemented in a standard 0.13 µm CMOS technology. A direct-conversion architecture for the 5 - 6 GHz band and a heterodyne architecture for a multi-band system are proposed. The most common receiver architectures are analyzed and the wave propagation effects are discussed. Then the most important receiver parameters are derived. Active and passive integrated components are investigated because understanding the device characteristic is a key requirement for a successful high frequency design. Finally, the multi-standard adaptive receiver concept is introduced. The choice of architecture, design and implementation of each of the receiver building blocks are discussed. The functionality of the 5 - 6 GHz receiver and the 24 GHz down-converter is demonstrated by the performance measurements. The main achievements of this work include: Firstly, a 5-6 GHz LNA integrated in 0.13 µm CMOS technology. The amplifier exhibits a gain of 16.5 dB, noise figure of 2.9 dB and 1 dB input compression point of -6.5dBm at power consumption of 7.5mW. The circuit features robust built-in input ESD protection. Secondly, a 5-6 GHz zero-IF receiver with analog pre-processing features a noise figure of 3.8 dB at the conversion gain of 43.4 dB. The channel select filter corner frequency is tunable to 6.5, 10, 20 and 50 MHz. The implemented analog pre-processing loop allows to adopt the linearity of the receiver to the input signal level. Thirdly, a 23-24 GHz tuned down-converter achieved the gain of 21.8 dB, noise figure of 6.8 dB and 1 dB input compression point of -16.7dBm at power consumption of 58.5mW.
This thesis presents the design and implementation of the RF power amplifiers in modern silicon based technologies. The main challenge is to include power amplifier on a single chip with output power level in watts, operating at high frequencies where the transit frequency (fT) is just a few times higher than the operating frequency. This work describes the design procedure for bipolar and CMOS transformer-based Class-A, Class-AB and Class-B power amplifiers. The design procedure is based on the HICUM for bipolar and BSIM4 for CMOS transistor models and is divided in four parts: •Building a one transistor prototype power amplifier which is based on the analytical analysis of the output characteristics and transistor model. •Load-pull simulation to define the final input and output impedances. •Derivation of the analytical equations for the transformer-based matching network. •Design of the final transformer-based push-pull power amplifier. A good agreement between the proposed analytical analysis and large-signal (harmonic balance) simulation results proofs usefulness of the proposed power amplifier design approach. Additionally, it shows the contribution of the separated devices at the final design that helps to find a technology limits in the current circuit design. The main achievements include: •A 2.4 GHz power amplifier in 0.13 um CMOS technology. An output power of 28 dBm is achieved with a power added efficiency of 48 % at a supply voltage of 1.2 V [Vasylyev 04]. •Two 17 GHz power amplifiers in 0.13 um CMOS technology (one fully integrated while the other with external matching network) with output power exceeding 50 mW. The former exhibits a power added efficiency of 9.3 % while the latter a 15.6 % power added efficiency [Vasylyev 06]. •A fully integrated K and Ka bands power amplifier in 0.13 um CMOS technology. A 13 dBm output power along with power added efficiency of 13 % is achieved at an operating frequency of 25.7 GHz with 1.2 V supply [Vasylyev 05,a]. •A fully integrated power amplifier based on a novel power combining transformer structure in 28 GHz-fT SiGe-bipolar technology. A 32 dBm output power along with power added efficiency of 30 % is achieved at an operating frequency of 2.12 GHz with 3.5 V supply [Vasylyev 05,b].