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The license-free 60 GHz band enables a new breed of wireless networks offering data rates in the range of one to a few Gigabit per second over short distances. This thesis investigates the performance of a 60 GHz system using coded OFDM modulation and directive antennas for the transmitter and receiver. The study includes the impact of the 60 GHz propagation channel, impairments of a frontend in Si-Ge technology and considerations with respect to an efficient implementation. A major part of the work consists in the specification of a physical layer, which is optimized for the given wireless link and enables an implementation with programmable logic devices at moderate clock speed. For the selection of a channel code, the performance of two coding schemes is compared for the 60 GHz channel. The first scheme consists of a standard convolutional code and an outer Reed-Solomon code, whereas the second scheme is made up of an LDPC code with similar complexity. The interleaving scheme for the convolutional code is optimized to yield best performance. Furthermore, algorithms are developed and simulated for all essential system components of the OFDM receiver. The implementation of these components is also considered. A new synchronization scheme is introduced, which offers a high degree of robustness at low complexity. In this scheme, the fine timing synchronization shares the same hardware resources as the channel estimator. This approach results in a significant reduction of chip area. A new tracking algorithm is developed, which adequately compensates for the fluctuations of carrier phase, timing and channel impulse response. Finally, the implementation of the FFT and Viterbi decoder is discussed. The system architecture of the receiver requires a high degree of parallel processing and uses a deep processing pipeline to keep the clock frequency low. It is shown how to combine the system components into an efficient system under these conditions. The performance of the complete system is investigated for the static and time-variant channel. It is shown that despite the low complexity and high latency, the system achieves good performance. The baseband processor has been realized as a narrowband version with 400 MHz channels and broadband version with 2 GHz channels and improved algorithms. This has been done on an FPGA platform.