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This dissertation presents a novel technique for enhancing the spurious-free dynamic range of radio monitoring receivers with a bandwidth of several gigahertz. The improvement is based on suppressing the discrete spurious signals that occur at higher drive levels in the output spectrum of the required broadband analog-to-digital converter. The achievable improvement of the spurious-free dynamic range is typically more than 20 dB, allowing better, gap-free monitoring of wide frequency ranges. The attenuation of the spurious signals is achieved by a unique combination of two separate analog-to-digital converters working in parallel and subsequent digital signal processing. The developed solution is not limited to broadband radio monitoring receivers but can generally suppress certain types of spurious signals generated during analog-to-digital conversion.
With further scaling of CMOS technology noise disturbance, mismatch and process variation become the major constraints of analog DC-DC converters. Consequently, digitally assisted DC-DC converters are coming in the focus of new systems, because they are easier to be configurated in the applications than the typical analog DC-DC converters, while being more robust against noise disturbance and process variation.
As interface devices between analog real world and digital signal processing, ADCs must be optimized for signals in digital DC-DC converters. But the existing synchronous ADCs, which require multiple clock cycles per conversion, as SAR and Pipeline ADCs, are not suitable for the application in DC-DC converters because of special signal characteristics. For stability reasons the digital feedback control in DC-DC converters requires a short group delay (dead time). So synchronous ADCs must be run at a sampling frequency as high as possible. But this approach results unfortunately in high power dissipation.
Compared to the above mentioned ADCs, the delta-encoded or Tracking ADC exhibits the shortest group delay by performing the data conversion only in one clock cycle. It makes the digital feedback control of DC-DC converters possible to response the output exactly and simultaneously. However, the synchronized Tracking ADC still has to cover the double of broad signal bandwidth of disturbance, which appears at the output of DC-DC converters occasionally, dissipating unnecessary excessive power.
This dissertation presents a new concept of Tracking ADC that selfadjusts the conversion rate depending on the slope of the input signal. For a slowly varying input, this Tracking ADC is self-clocked at a low frequency in normal mode, but once the signal varies fast and the slope exceeds a defined threshold, the conversion rate of the ADC is increased to track the signal accurately. By using the proposed solution not only the issue of input slope overload for typical Tracking ADCs is significantly improved, but also the average sampling rate is decreased. Therefore, the power dissipation of the proposed ADC is also reduced.
As a proof of this concept, a 6-bit Tracking ADC with transient-driven self-clocking is implemented in 0.13μm CMOS technology. The prototype of the ADC occupies an area of 400μm×200μm. The maximum power dissipation is 84μW at a supply voltage of 1.4V, when operated at 50MS/s. The integral nonlinearity (INL) is better than 0.5LSB, and the effective number of bits (ENOB) at the sampling frequency of 12.5MHz is 4.4 bits, where the ideal ENOB is limited to 5 bits for 6-bit Tracking ADCs.
High-speed data capturing components for Super Resolution Maximum Length Binary Sequence UWB Radar
(2011)
Within framework of UKoLoS project the new Super Resolution Maximum Length Binary Sequence UWB Radar (M-sequence radar) was developed. The radar consists of an M-sequence generator, transmitter front-end, receiver front-end, data capturing device and data processing blocks, whose design responsibilities were carried out by four institutions. In this thesis the design and measurements of the data capturing device components is described. Logically the data capturing device can be divided into three parts; a capturing part, realized with the high-speed analog-to-digital converter, a predictor, realized with the high-speed digital-to-analog converter and a subtraction amplifier, which in this particular work is integrated into the receiver front-end. The main challenge of the work is to implement the A/D converter, which works at full speed of the radar. Despite the radar architecture allows capturing data with undersampling, it leads to waste of transmitted energy. Therefore the ADC has to capture reflected signal with the full system clock rate of 10 GHz and should have a full Nyquist 5 GHz effective resolution bandwidth. Implementation of the conventional 4-bit full flash ADC with specified bandwidth is not possible in the IHP SiGe BiCMOS technology because some critical blocks, namely the reference network, can not achieve 5 GHz effective resolution bandwidth. To overcome this problem a new configuration of the differential reference network is proposed. The new reference network has a segmented, free configurable architecture. As extreme case it can be realized as a full parallel network and in such configuration the maximal bandwidth can be achieved. The proposed network was implemented in the A/D converter and measured. The bandwidth of the ADC with new network is several times higher than the bandwidth of the conventional ADC,while keeping power dissipation the same. Further the proposed network has possibility to equalize the bandwidth in each output node and in that way optimize overall power dissipation. The other advantage is the possibility of electronic calibration of separate voltage shift in the network. The second component of the data capturing device is the D/A converter, which is required to have the accuracy which corresponds to full accuracy of the data capturing device, better than 0.2% in our case. Measurements showed that error due to mismatch of the components was 10 times higher than required. To meet the accuracy specification an external off-line calibration of the DAC was implemented. Using calibration the predictor errors less than 0.15% were achieved.