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Wireless communication has become an indispensable part of our life and the demand for achieving higher throughput with lower energy consumption is ever growing. The ambitious throughput of 100 Gb/s and beyond is now becoming a modest goal thanks to comprehensive advances in transmission technologies and protocols. One important aspect of these advances is with regard to channel coding methods and the ability to detect and correct errors at the receiver. Computations needed by such methods become generally more complicated as they become more powerful in their performance. This imposes a great challenge for researchers attempting to devise practical methods for encoding and decoding Forward-error Correction (FEC) techniques tailored for high-throughput scenarios.
In this work we focus on high-throughput Quasi-Cyclic LDPC (QC-LDPC) codes, as they have been selected as one of the main FEC techniques for the two major next generation wireless technologies, namely Wi-Fi 6 (IEEE 802.11ax) and 5G. Our target is to develop complete encoding and decoding design for these codes in order to reach the throughput of 100 Gb/s with affordable power consumption. Toward this goal, we investigate first the appropriate encoder design for these codes which can be used at such high data-rate with reasonably low power consumption. Then we propose several novel ideas for improving the decoding performance and complexity of QC-LDPC codes. The proposed novel ideas collectively facilitate a decoder able to run at 50 Gb/s with less than 12 pJ/b energy consumption for a Latin squares QC-LDPC code. All the proposed methods are practical and implementable and their effectiveness are showcased by either Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) synthesis.
Mixed signal integrated circuits (MSICs) contain both analog and digital circuitry, integrated together on the same die. While this integration brings many benefits, it also gives rise to the issue of substrate noise coupling between the noisy digital circuitry and noise-sensitive analog circuitry. In order to counteract this issue, various substrate noise reduction methodologies had been developed so far. This thesis explores a new approach in substrate noise reduction – using a GALS (globally-synchronous, locally-asynchronous) design strategy for the digital part of a MSIC, in order to reduce the noise generation at its source. GALS architectures consist of several locally synchronous modules (LSMs) which communicate asynchronously to each other. By converting an initially synchronous architecture of digital circuitry into a GALS architecture, simultaneous switching noise generated by this circuitry can be reduced. While GALS had already been used for reducing other types of simultaneous switching noise, this is, to the best of the author’s knowledge, the first attempt to develop a GALS-based methodology for substrate noise reduction. In order to be able to theoretically analyze GALS-based methodologies for substrate noise suppression, corresponding models at high abstraction level for substrate noise generation and substrate noise propagation in lightly doped substrates (which is a type of substrate mostly used for MSICs) have been developed. These models have further been used for developing two new GALS-based substrate noise reduction methodologies: harmonic-balanced plesiochronous GALS partitioning (HB) and harmonic-and-area-based plesiochronous GALS partitioning with power domain separation (HAB). A theoretical analysis has shown that HB can reach substrate noise attenuation of up to 20log(M), where M is the number of LSMs of the resulting GALS system. On the other hand, the attenuation achievable by HAB depends on the distribution of switching current harmonics and area among the partitions, as well as from the substrate itself. For each of the two methodologies, a suitable partitioning procedure for a practical application has been developed; these partitionig procedures have been numerically evaluated in MATLAB. HB has further been embedded within the EMIAS CAD tool, where it has been evaluated on a real design example – a wireless sensor node. A special case of HAB for low frequencies has been applied for developing a test chip called SGE (power domain Separation and Galsification Experiment). The measurements on silicon have proved the applicability of the methodology.
Factory automation applications require a communication system that concurrently supports them with determinism, reliability, short communication cycles, and precise synchronization as well as mobility and extensibility. However, neither currently employed wired nor available wireless communication networks support all of these requirements at once. On the one hand, wired networks lack mobility and extensibility. On the other hand, wireless networks do not support reliability or determinism due to the stochastic nature of wireless channels. Moreover, none of the available wireless networks enable transmission latencies of 1 ms and below. Therefore, they cannot support the required short communication cycles. However, various research initiatives and the currently developed 5G standard promise to overcome these limitations at least partially.
Nevertheless, even a corresponding wireless network will not directly replace all wired connections, but will initially be used for subsections of the data transmission, where e.g. mobility is of utmost importance. Accordingly, cascaded communication networks consisting of hierarchically ordered, wired and wireless subnetworks will emerge. In this thesis, we investigate effects and dependencies of such a cascading for the real-time communication of factory automation applications. Therefore, we have to find methods to interconnect arbitrary wired and wireless communication networks such that we can maintain the reliable real-time performance of wired subnetworks and the mobility of wireless subnetworks without, or at most with minimal performance degradation. Ideally, with a cascaded network, no hardware or software adjustments will be necessary compared to the individual networks deployed today.
Based on a delimiting review of different application areas and a dedicated use case analysis of typical factory automation applications, we derive the most challenging requirements that have to be fulfilled by cascaded communication networks. According to this review, we present several methods to reduce the overall transmission latency in cascaded networks. Starting with analyzing different interface concepts and continuing with frame conversion methods, we achieve a decision-making basis to select dedicated subnetworks for a cascaded network that can be used for closed-loop control applications. Additionally, we develop methods to optimize the parametrization of individual subnetworks with respect to the overall communication, such that the end-to-end transmission latency can be drastically reduced. For verification, we design a generic model for analyzing the timing behavior of arbitrary communication networks and verify it based on an analysis of a machine tool application scenario. Additional measurements based on a real demonstrator implementation corroborate that, in industrial application, cascaded communication networks can provide competitive performance compared to the currently used wired networks.