Low latency reconfiguration mechanism for fine-grained processor internal functional units

  • The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. TheThe strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.show moreshow less

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Metadaten
Author: Segabinazzi Ferreira, RaphaelORCiD, Nolte, Jörg
URN:urn:nbn:de:kobv:co1-opus4-50497
DOI:https://doi.org/10.1109/LATW.2019.8704560
Parent Title (English):Proceedings of the 2019 IEEE Latin American Test Symposium (LATS)
Document Type:Conference Proceeding
Language:English
Year of Completion:2019
Release Date:2020/01/22
Tag:Fine-grained; Functional units low latency; Reconfiguration; Software
GND Keyword:Latenzzeit <Informatik>; Mikroprozessor; Rekonfiguration
Source:R. Segabinazzi Ferreira and J. Nolte: Low latency reconfiguration mechanism for fine-grained processor internal functional units - in: 2019 IEEE Latin American Test Symposium (LATS), Santiago - CL, March 11-13, 2019
Institutes:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Verteilte Systeme und Betriebssysteme
Licence (German):Keine Lizenz vergeben. Es gilt das deutsche Urheberrecht.