TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Low latency reconfiguration mechanism for fine-grained processor internal functional units N2 - The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features. KW - Functional units low latency KW - Fine-grained KW - Reconfiguration KW - Software KW - Rekonfiguration KW - Mikroprozessor KW - Latenzzeit Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50497 ER - TY - CHAP A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Reconfiguration KW - Run-Time KW - Modular redundancy KW - Mixed-criticality KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Redundanz Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-52031 SN - 978-1-7281-6958-3 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time hardware reconfiguration of functional units to support mixed-critical applications N2 - System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements. KW - Reconfiguration KW - Functional units KW - Fine-grained KW - Mixed-criticality KW - Run-time KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Fehlererkennung Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-51804 ER -