TY - RPRT A1 - Nolte, Jörg T1 - 12. GI/ITG Fachgespräch Sensornetze N2 - Drahtlose Sensornetze stellen eine vielversprechende Technologie zur Beobachtung und Beeinflussung von Vorgängen in der realen Welt dar. Autonome Sensorknoten nehmen dabei Parameter der Umwelt durch Sensoren wahr und können diese durch Aktoren beeinflussen. Viele solcher autonomen und ressourcenbeschränkten Knoten kooperieren dabei mittels drahtloser Kommunikation. Die Eigenschaften dieser Knoten und Netze implizieren eine Vielzahl von neuartigen Herausforderungen, die sich in einer regen Forschungsaktivität widerspiegeln. Ziel dieser Reihe von Fachgesprächen ist es, Wissenschaftlerinnen und Wissenschaftlern aus Hochschule und Industrie die Möglichkeit zu einem informellen Gedankenaustausch zu geben und die Kooperation in diesem multidisziplinären Forschungsbereich zu verstärken. T3 - Computer science reports / Institut für Informatik - 2013,03 KW - Drahtloses Sensorsystem Y1 - 2013 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus-28986 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Low latency reconfiguration mechanism for fine-grained processor internal functional units N2 - The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features. KW - Functional units low latency KW - Fine-grained KW - Reconfiguration KW - Software KW - Rekonfiguration KW - Mikroprozessor KW - Latenzzeit Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50497 ER - TY - CHAP A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Reconfiguration KW - Run-Time KW - Modular redundancy KW - Mixed-criticality KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Redundanz Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-52031 SN - 978-1-7281-6958-3 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. KW - Self-awareness KW - Configurable circuits KW - Fault tolerant KW - Operation modes KW - Integrierte Schaltung KW - Konfiguration KW - Fehlertoleranz Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50503 SN - 978-3-902457-54-7 ER - TY - JOUR A1 - Kurth, Winfried A1 - Bachmann, Peter A1 - Heiner, Monika A1 - König, Hartmut A1 - Kraemer, Rolf A1 - Lewerentz, Claus A1 - Nolte, Jörg A1 - Thalheim, Bernhard A1 - Vierhaus, Heinrich Theodor A1 - Braunmühl, Burchard von A1 - Wagner, Gerd T1 - Jahresbericht 2003/2005 / Institut fuer Informatik, Informations- und Medientechnik T1 - Annual Report 2003/2005 / Department for Computer Science, Information and Media Technology N2 - Selbstdarstellung des Instituts für Informatik, Informations- und Medientechnik der BTU Cottbus und Berichte der Lehrstühle für die Jahre 2003, 2004 und 2005. N2 - Presentation of the Department for Computer Science, Information and Media Technology of the BTU Cottbus and reports of the chairs at the department for the years 2003, 2004 and 2005. T3 - Jahresbericht / Institut für Informatik, Informations- und Medientechnik - 2003/2005 KW - Cottbus / Technische Universität KW - Bericht KW - Informatik KW - Informations- und Medientechnik KW - BTU Cottbus KW - Computer Science KW - Information Technology KW - Media Technology KW - BTU Cottbus Y1 - 2006 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus-3488 ER - TY - JOUR A1 - Thalheim, Bernhard A1 - Heiner, Monika A1 - Kurth, Winfried A1 - Bachmann, Peter A1 - König, Hartmut A1 - Lewerentz, Claus A1 - Vierhaus, Heinrich Theodor A1 - Braunmühl, Burchard von A1 - Nolte, Jörg T1 - Jahresbericht 2001/2002 / Institut für Informatik T1 - Annual Report 2001/2002 / Department for Computer Science N2 - Selbstdarstellung des Instituts für Informatik der BTU Cottbus und Berichte der Lehrstühle für die Jahre 2001 und 2002. N2 - Presentation of the Department for Computer Science of the BTU Cottbus and reports of the chairs at the department for the years 2001 and 2002. T3 - Jahresbericht / Institut für Informatik - 2001/2002 KW - Cottbus / Technische Universität KW - Bericht KW - Informatik KW - BTU Cottbus KW - Computer Science KW - BTU Cottbus Y1 - 2003 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus-3527 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time hardware reconfiguration of functional units to support mixed-critical applications N2 - System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements. KW - Reconfiguration KW - Functional units KW - Fine-grained KW - Mixed-criticality KW - Run-time KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Fehlererkennung Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-51804 ER - TY - CHAP A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Hasani, Alireza A1 - Kraemer, Rolf A1 - Lopacinsiki, Lukasz T1 - End2End100 : communication protocol processing for ultra high data rates T1 - End2End100 : Kommunikations-Protokoll–Prozessierung für ultrahohe Datenraten T2 - Wireless 100 Gbps and beyond : architectures, approaches and findings of German Research Foundation (DFG) Priority Programme SPP1655 N2 - In 2012 a group of researchers proposed a basic research initiative to the German Research Foundation (DFG) as a special priority project (SPP) with the name: Wireless 100 Gbps and beyond. The main goal of this initiative was the investigation of architectures, technologies and methods to go well beyond the state of the art. The target of 100 Gbps was set far away from the (at that time) achievable 1 Gbps such that it was not possible to achieve promising results just by tuning some parameters. We wanted to find breakthrough solutions. When we started the work on the proposal we discussed the challenges to be addressed in order to advancing the wireless communication speed significantly. Having the fundamental Shannon boundary in mind we discussed how to achieve the 100 Gbps speed. N2 - Angesichts der rapiden Entwicklung der Funkkommunikation hat die Deutsche Forschungsgemeinschaft im Jahr 2012 ein Schwerpunktprogramm mit dem Titel "Wireless 100 Gbps and beyound" (dt.: Drahtloskommunikation mit 100 Gbps und mehr) gestartet. Diese Initiative zielte auf neue Lösungen, Methoden und neues Wissen zur Lösung des Problems des kontinuierlichen Bedarfs an immer höheren Datenraten im Bereich der Funkkommunikation. Eine international besetze Jury hat etliche Projektvorschläge evaluiert, aus denen 11 Projekte ausgewählt und über zweimal 3 Jahre von Mitte 2013 bis Mitte 2019 gefördert wurden. Das vorliegende Buch versammelt die Ansätze, Architekturen und Erkenntnisse der Projekte. Es überspannt einen breiten Themenbereich, angefangen mit speziellen Fragen der physikalischen Übertragung, des Antennendesigns und der HF-Eingangs-Architekturen für unterschiedliche Frequenzbereiche bis 240 GHz. Darüber hinaus beschreibt das Buch Ansätze für Ultra-Hochgeschwindigkeits-Funksysteme, deren Basisbandverarbeitung, Kodierung sowie mögliche Umsetzungen. Nicht zuletzt wurden auch Fragen des Protokolldesigns behandelt, um eine enge Integration in moderne Computersysteme zu erleichtern. KW - 100 Gbps KW - Wireless KW - Drahtlos KW - End2End100 KW - Communication protocol processing KW - Kommunikations-Protokoll–Prozessierung KW - Drahtloses Sensorsystem KW - Hochfrequenztechnik KW - Antenne KW - Terahertzbereich KW - Energieffizienz Y1 - 2020 U6 - https://doi.org/10.26127/BTUOpen-5916 SP - 359 EP - 396 ER -