TY - CHAP A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Reconfiguration KW - Run-Time KW - Modular redundancy KW - Mixed-criticality KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Redundanz Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-52031 SN - 978-1-7281-6958-3 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER - TY - THES A1 - Segabinazzi Ferreira, Raphael T1 - Run-time redundancy management of processor functional units for mixed-critical scenarios T1 - Laufzeit-Redundanzmanagement von Prozessor-Funktionseinheiten für gemischtkritische Szenarien N2 - Since electronics started to scale down, a growing concern about the reliability of these electronic devices has emerged. At the same time, the increased demand for high performance within the safety- and mixed-critical domains, such as the aerospace and automotive industry, motivated a shift from previous consolidated and mature technology to the new cutting edge devices with smaller feature sizes. Therefore, there is a need to improve the fault tolerance of these high-end devices so that minimum failure rates can be obeyed. Although redundancy has been a great solution for these problems, their drawbacks such as power and area overheads must be watched carefully, so that per-unit price does not extrapolate affordable limits, and the redundancy does not add more sources of error than it improves the fault tolerance. This thesis proposes an approach for run-time management of redundancy among the processor internal Functional Units (FUs) within mixed-critical scenarios, tackling the compensation of the trade-offs between fault-tolerance, power consumption, hardware usage (ageing), and hardware area (cost). With these objectives in mind, this thesis presents a concept for a dynamic processor architecture capable to enable and disable redundancy of FUs on-demand, and a software mechanism for criticality-aware management of these units for mixed-critical processes within an Operating System (OS). For this purpose, a processor design was extended with a few additional instructions that enabled different replication schemes in the processor at run-time. Furthermore, a compatible Real-Time Operating System (RTOS) is also extended to enable the desired criticality-aware management of units. Evaluating the implemented test platform when the extended processor was running bare-metal code, the latency to shift between different replication schemes was of only one instructions cycle. Furthermore, when the processor was running the adapted RTOS, the run-time overhead over the latency to switch between processes remained below 2.5%. Meanwhile, resulting from the processor extensions, the hardware overhead remained smaller than standard full core replication schemes such as core lock-step approaches. Regarding fault tolerance, the expected failure rate of the FUs module decreased by approximately 80% when its FUs were configured with Triple Modular Redundancy (TMR). Furthermore, when considering the whole area of the processor core, its respective failure rate decreased by about 15% when configured these units with the same triplication scheme. Finally, it is also presented that the run-time management of FUs was likewise able to decrease the power consumption and hardware ageing for the proposed mixed-critical scenario. After all, we can say that the concept can increase fault tolerance on-demand of a processor design with moderately low hardware overhead, while it also minimises the power consumption and hardware usage (ageing) for its intended mixed-critical scenario. N2 - Seit die Elektronik immer kleiner wird, ist eine wachsende Besorgnis über die Zuverlässigkeit dieser elektronischen Geräte entstanden. Gleichzeitig motivierte die gestiegene Nachfrage nach hoher Leistung in sicherheits- und gemischt kritischen Bereichen wie der Luft- und Raumfahrt und Automobilindustrie zu einer Umstellung von früher konsolidierter und ausgereifter Technologie auf die neuen Spitzengeräte mit kleineren Strukturgrößen. Daher muss die Fehlertoleranz dieser High-End-Geräte verbessert werden, damit minimale Ausfallraten eingehalten werden können. Obwohl Redundanz eine großartige Lösung für diese Probleme ist, müssen ihre Nachteile wie Energie- und Flächen-Overhead sorgfältig beobachtet werden, damit der Preis pro Einheit nicht erschwingliche Grenzen extrapoliert und die Redundanz nicht mehr Fehlerquellen hinzufügt, als sie verbessert Fehlertoleranz. Vor diesem Hintergrund stellt diese Arbeit ein Konzept für eine dynamische Prozessorarchitektur vor, die in der Lage ist, die Redundanz von Funktionseinheiten (“Functional Units”, FUs) bei Bedarf zu aktivieren und zu deaktivieren, sowie einen Softwaremechanismus zur kritikalitätsbewussten Verwaltung dieser Einheiten für gemischt kritische Prozesse innerhalb eines Betriebssystems (“Operating System”, OS). Dazu wurde ein Prozessordesign um einige zusätzliche Anweisungen erweitert, die zur Laufzeit unterschiedliche Replikationsschemata im Prozessor ermöglichen. Darüber hinaus wird auch ein kompatibles Echtzeit-Betriebssystem (“Real-Time Operating System”, RTOS) erweitert, um die gewünschte kritikalitätsbewusste Verwaltung von Einheiten zu ermöglichen. Die Rekonfiguration des Prozessors erfordert nur einen Befehlszyklus, der gesamte zusätzliche overhead für den Prozesswechsel beträgt weniger als 2,5%. In der Zwischenzeit blieb der Hardware-Overhead aufgrund der Prozessorerweiterungen kleiner als bei standardmäßigen vollständigen Kernreplikationsschemata, wie z. B. Core-Lock-Step-Ansätzen. In Bezug auf die Fehlertoleranz verringerte sich die erwartete Ausfallrate des FU-Moduls um etwa 80%, wenn es mit Dreifacher Modularer Redundanz (“Triple Modular Redundancy”, TMR) konfiguriert wurde. Darüber hinaus verringerte sich bei Betrachtung der gesamten Fläche des Prozessorkerns die jeweilige Ausfallrate um etwa 15%, wenn die Einheiten mit demselben Verdreifachungsschema konfiguriert wurden. Abschließend wird auch dargestellt, dass das Laufzeitmanagement von FUs den Stromverbrauch und die Hardwarealterung für das vorgeschlagene gemischt-kritische Szenario ebenfalls verringern konnte. Schließlich können wir sagen, dass das Konzept die Fehlertoleranz eines Prozessordesigns mit mäßig niedrigem Hardware-Overhead bei Bedarf erhöhen kann, während es auch den Stromverbrauch und die Hardwarenutzung (Alterung) für das beabsichtigte gemischt-kritische Szenario minimiert. KW - Mixed-critical scenario KW - Redundancy KW - Fault-tolerance KW - Run-time KW - Fehlertoleranz KW - Redundanz KW - Funktionseinheit KW - Mikroprozessor KW - Laufzeit KW - Gemischtkritische Szenarien KW - Laufzeit KW - Redundanz Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-58886 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. KW - Self-awareness KW - Configurable circuits KW - Fault tolerant KW - Operation modes KW - Integrierte Schaltung KW - Konfiguration KW - Fehlertoleranz Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50503 SN - 978-3-902457-54-7 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Low latency reconfiguration mechanism for fine-grained processor internal functional units N2 - The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features. KW - Functional units low latency KW - Fine-grained KW - Reconfiguration KW - Software KW - Rekonfiguration KW - Mikroprozessor KW - Latenzzeit Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50497 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time hardware reconfiguration of functional units to support mixed-critical applications N2 - System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements. KW - Reconfiguration KW - Functional units KW - Fine-grained KW - Mixed-criticality KW - Run-time KW - Rekonfiguration KW - Laufzeit KW - Funktionseinheit KW - Fehlererkennung Y1 - 2020 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-51804 ER -