TY - THES A1 - Krstic, Milos T1 - Request-driven GALS technique for datapath architectures N2 - In this thesis a novel Globally Asynchronous Locally Synchronous (GALS) technique applicable to wireless communication systems and generally to datapath architectures is presented. The proposed concept is intended for point-to-point communication with very intensive but bursty data transfer. This concept is based on a request-driven operation of locally synchronous modules. The key idea is that a module can use the input request signal as its clock while receiving a burst of data. The developed GALS technique is applied to the design of an IEEE 802.11a compliant baseband processor with the aim to alleviate the problems of system integration, power consumption and electro-magnetic interference. The GALS design was compared with a synchronous version of the baseband processor. In our experimental setup we have measured a 1% reduction in dynamic power consumption, 30% reduction in instantaneous supply voltage variations, and 5 dB reduction in spectral noise. N2 - In dieser Doktorarbeit wird eine global asynchrone, lokal synchrone (GALS) Technik, die auf drahtlose Kommunikationssysteme und im Allgemeinen auf Datenpfad-Architekturen anwendbar ist, dargestellt. Das vorgeschlagene Konzept ist für Punkt-zu-Punkt organisierte Strukturen mit sehr intensiver, aber Block organisierter Datenübertragung vorgesehen. Dieses Konzept basiert auf einem Request-driven Betrieb der lokalen synchronen Blöcke. Die Schlüsselidee ist, dass ein Modul das Request-Signal als Taktsignal beim Empfangen eines Blocks von Daten benutzen kann. Die entwickelte GALS-Technik wird auf das Design eines IEEE 802.11a kompatiblen Basisbandprozessors angewendet, um die Probleme System-Integration, Leistungsaufnahme und elektromagnetische Störung zu vermindern. Das GALS-Design wird mit einer synchronen Version des Basisbandprozessors verglichen. Unsere Messungen ergaben eine Verringerung des dynamischen Energieverbrauchs um 1%, eine Verringerung von Versorgungsspannungs-Schwankungen um 30% und eine Reduktion des spektralen Rauschens um 5 dB. KW - GAL KW - GALS KW - Systemintegration KW - Asynchroner Entwurf KW - EMI KW - BIST Y1 - 2006 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-000000888 ER - TY - CHAP A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. KW - Self-awareness KW - Configurable circuits KW - Fault tolerant KW - Operation modes KW - Integrierte Schaltung KW - Konfiguration KW - Fehlertoleranz Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus4-50503 SN - 978-3-902457-54-7 ER -