@phdthesis{Gypser2022, author = {Gypser, Philipp}, title = {Mechanisms for energy-efficient processor allocation and redistribution on manycore systems}, doi = {10.26127/BTUOpen-6385}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-63853}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {Multi- and manycore processors promise to combine high overall peak performance with moderate power consumption to meet the constantly growing demand for computational power under the energy constraints of today's CMOS technology. Future systems with manycore processors are expected to contain a huge amount of cores, which exceeds the number of processes that will run simultaneously. Consequently, processor time sharing approaches, that introduce significant overhead from regular context switches in common OS, will no longer be necessary. This work investigates mechanisms for scalable and energy-efficient spatial partitioning of multi- and manycore processor systems. In addition, it explores the implications of exclusive processor core allocation to user processes due to the absence of temporal multiplexing and offers approaches to ease the adaptation to the new programming model. The proposed mechanisms achieved fast thread allocation which motivates applications for dynamic thread allocation and benefits performance as well as energy efficiency. The efficiency control and resource revocation mechanisms detect and prevent wasteful and inefficient resource occupation from poorly optimized or malicious processes. In this way, the global efficiency of the system is optimized. The dynamic processing resource allocation and revocation handling has been integrated into a task parallel runtime system, to disburden the application programmer from manual implementation and to increase productivity.}, subject = {Manycore; Operating systems; Online profiling; Energy efficiency; Dynamic partitioning; Vielkernprozessor; Betriebssysteme; Profiling; Energie-Effizienz; Dynamische Partitionierung; Mehrkernprozessor; Betriebssystem; Partionierung; Energieeffizienz}, language = {en} } @phdthesis{SegabinazziFerreira2022, author = {Segabinazzi Ferreira, Raphael}, title = {Run-time redundancy management of processor functional units for mixed-critical scenarios}, doi = {10.26127/BTUOpen-5888}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-58886}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {Since electronics started to scale down, a growing concern about the reliability of these electronic devices has emerged. At the same time, the increased demand for high performance within the safety- and mixed-critical domains, such as the aerospace and automotive industry, motivated a shift from previous consolidated and mature technology to the new cutting edge devices with smaller feature sizes. Therefore, there is a need to improve the fault tolerance of these high-end devices so that minimum failure rates can be obeyed. Although redundancy has been a great solution for these problems, their drawbacks such as power and area overheads must be watched carefully, so that per-unit price does not extrapolate affordable limits, and the redundancy does not add more sources of error than it improves the fault tolerance. This thesis proposes an approach for run-time management of redundancy among the processor internal Functional Units (FUs) within mixed-critical scenarios, tackling the compensation of the trade-offs between fault-tolerance, power consumption, hardware usage (ageing), and hardware area (cost). With these objectives in mind, this thesis presents a concept for a dynamic processor architecture capable to enable and disable redundancy of FUs on-demand, and a software mechanism for criticality-aware management of these units for mixed-critical processes within an Operating System (OS). For this purpose, a processor design was extended with a few additional instructions that enabled different replication schemes in the processor at run-time. Furthermore, a compatible Real-Time Operating System (RTOS) is also extended to enable the desired criticality-aware management of units. Evaluating the implemented test platform when the extended processor was running bare-metal code, the latency to shift between different replication schemes was of only one instructions cycle. Furthermore, when the processor was running the adapted RTOS, the run-time overhead over the latency to switch between processes remained below 2.5\%. Meanwhile, resulting from the processor extensions, the hardware overhead remained smaller than standard full core replication schemes such as core lock-step approaches. Regarding fault tolerance, the expected failure rate of the FUs module decreased by approximately 80\% when its FUs were configured with Triple Modular Redundancy (TMR). Furthermore, when considering the whole area of the processor core, its respective failure rate decreased by about 15\% when configured these units with the same triplication scheme. Finally, it is also presented that the run-time management of FUs was likewise able to decrease the power consumption and hardware ageing for the proposed mixed-critical scenario. After all, we can say that the concept can increase fault tolerance on-demand of a processor design with moderately low hardware overhead, while it also minimises the power consumption and hardware usage (ageing) for its intended mixed-critical scenario.}, subject = {Mixed-critical scenario; Redundancy; Fault-tolerance; Run-time; Fehlertoleranz; Redundanz; Funktionseinheit; Mikroprozessor; Laufzeit; Gemischtkritische Szenarien; Laufzeit; Redundanz}, language = {en} }