@phdthesis{Vasylyev2006, author = {Vasylyev, Andriy}, title = {Integrated RF power amplifier design in Silicon-based technologies}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-202}, school = {BTU Cottbus - Senftenberg}, year = {2006}, abstract = {This thesis presents the design and implementation of the RF power amplifiers in modern silicon based technologies. The main challenge is to include power amplifier on a single chip with output power level in watts, operating at high frequencies where the transit frequency (fT) is just a few times higher than the operating frequency. This work describes the design procedure for bipolar and CMOS transformer-based Class-A, Class-AB and Class-B power amplifiers. The design procedure is based on the HICUM for bipolar and BSIM4 for CMOS transistor models and is divided in four parts: •Building a one transistor prototype power amplifier which is based on the analytical analysis of the output characteristics and transistor model. •Load-pull simulation to define the final input and output impedances. •Derivation of the analytical equations for the transformer-based matching network. •Design of the final transformer-based push-pull power amplifier. A good agreement between the proposed analytical analysis and large-signal (harmonic balance) simulation results proofs usefulness of the proposed power amplifier design approach. Additionally, it shows the contribution of the separated devices at the final design that helps to find a technology limits in the current circuit design. The main achievements include: •A 2.4 GHz power amplifier in 0.13 um CMOS technology. An output power of 28 dBm is achieved with a power added efficiency of 48 \% at a supply voltage of 1.2 V [Vasylyev 04]. •Two 17 GHz power amplifiers in 0.13 um CMOS technology (one fully integrated while the other with external matching network) with output power exceeding 50 mW. The former exhibits a power added efficiency of 9.3 \% while the latter a 15.6 \% power added efficiency [Vasylyev 06]. •A fully integrated K and Ka bands power amplifier in 0.13 um CMOS technology. A 13 dBm output power along with power added efficiency of 13 \% is achieved at an operating frequency of 25.7 GHz with 1.2 V supply [Vasylyev 05,a]. •A fully integrated power amplifier based on a novel power combining transformer structure in 28 GHz-fT SiGe-bipolar technology. A 32 dBm output power along with power added efficiency of 30 \% is achieved at an operating frequency of 2.12 GHz with 3.5 V supply [Vasylyev 05,b].}, subject = {Siliciumbauelement; Radiofrequenzbereich; Verst{\"a}rker; Leistungsverst{\"a}rker; CMOS; Power amplifier; CMOS}, language = {en} } @phdthesis{Debski2007, author = {Debski, Wojciech Andrzej}, title = {Multi-band adaptive WLAN receivers in 0.13 µm CMOS}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-3689}, school = {BTU Cottbus - Senftenberg}, year = {2007}, abstract = {This work demonstrates the design and implementation of a multi-band multi-standard WLAN system consisting of a 5 - 6 GHz receiver and a 24 GHz down-converter. The main challenges are high frequency, broadband, and adaptive operation, power consumption and high integration level. This thesis introduces a multi-standard adaptive receiver concept to fulfill those requirements. The receivers are implemented in a standard 0.13 µm CMOS technology. A direct-conversion architecture for the 5 - 6 GHz band and a heterodyne architecture for a multi-band system are proposed. The most common receiver architectures are analyzed and the wave propagation effects are discussed. Then the most important receiver parameters are derived. Active and passive integrated components are investigated because understanding the device characteristic is a key requirement for a successful high frequency design. Finally, the multi-standard adaptive receiver concept is introduced. The choice of architecture, design and implementation of each of the receiver building blocks are discussed. The functionality of the 5 - 6 GHz receiver and the 24 GHz down-converter is demonstrated by the performance measurements. The main achievements of this work include: Firstly, a 5-6 GHz LNA integrated in 0.13 µm CMOS technology. The amplifier exhibits a gain of 16.5 dB, noise figure of 2.9 dB and 1 dB input compression point of -6.5dBm at power consumption of 7.5mW. The circuit features robust built-in input ESD protection. Secondly, a 5-6 GHz zero-IF receiver with analog pre-processing features a noise figure of 3.8 dB at the conversion gain of 43.4 dB. The channel select filter corner frequency is tunable to 6.5, 10, 20 and 50 MHz. The implemented analog pre-processing loop allows to adopt the linearity of the receiver to the input signal level. Thirdly, a 23-24 GHz tuned down-converter achieved the gain of 21.8 dB, noise figure of 6.8 dB and 1 dB input compression point of -16.7dBm at power consumption of 58.5mW.}, subject = {Drahtloses lokales Netz; CMOS-Schaltung; WLAN; Adaptive Empf{\"a}nger; CMOS; WLAN; Adaptive receiver; CMOS}, language = {en} }