@misc{AlpirezBock2015, type = {Master Thesis}, author = {Alpirez Bock, Estuardo}, title = {SCA resistent implementation of the Montgomery kP-algorithm}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-36288}, school = {BTU Cottbus - Senftenberg}, year = {2015}, abstract = {Mathematically, cryptographic approaches are secure. This means that the time an attacker needs for finding the secret by brute forcing these approaches is about the time of the existence of our world. Practically, an algorithm implemented in hardware is a device that generates a lot of additional data during the calculation process. Its power consumption, electromagnetic radiation, etc. can be measured, saved and analysed for key extraction. Such attacks are called side channel analysis attacks and are significant threats when applying cryptographic algorithms. By considering these attacks when implementing a cryptographic algorithm, it is possible to design an implementation that is more resistant against them. The goal of this thesis was to design a methodology to securely implement the Montgomery kP-operation using an IHP implementation as a starting point. In addition, the area and energy consumption of the secure Montgomery kP-multiplier should still be highly efficient. The resistance against power analysis attacks of two different IHP ECC implementations was analysed in this thesis. A horizontal power analysis attack using the difference-of-means test was performed with the goal of finding potential leakage sources exploited in side channel analysis attacks, i.e. finding the reasons of a correct extraction of the cryptographic key. For both analysed ECC designs, four key candidates were extracted with a correctness of 90\% or more. Through analysis of the implemented Montgomery kP-algorithm's functionality and its power consumption, it was established that the algorithm's operation execution flow was the main cause of the implementations' vulnerability. Thus, a design methodology consisting in changing the Montgomery kP-algorithm operation flow was developed. As a result, the re-designed implementations do not deliver any correctly extracted key candidates whenever the difference-of-means test is performed on them. These re-designs implied an increase on the chip area by about 5\% for each implementation. The execution time needed for performing a complete kP-operation was reduced for both designs. Thereby one implementation's execution time was reduced by 12\% in comparison to its original version and even though its power consumption was increased by 9\%, its energy consumption per kP-operation was reduced by 4.5\%.}, subject = {Side channel analysis; Elliptic curve cryptography; Power analysis; Difference-of-means test; Elliptic curve point multiplication; Elliptische Kurve; Kryptologie}, language = {en} } @phdthesis{Brzozowski2012, author = {Brzozowski, Marcin}, title = {Energy-efficient means to support short end-to-end delays in wireless sensor networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-25299}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {This work addresses tough challenges of sensor network applications with Quality of Service requirements. That is, nodes must work with batteries for a long time, support short end-to-end delays and robust communication in multi-hop networks. It starts with presenting previous research efforts that address such challenges. For instance, many Medium Access Control (MAC) protocols keep nodes mostly sleeping to save energy and synchronize wake-up times for communication. Although such protocols offer short end-to-end delays, they still suffer from long idle listening and shortened lifetimes. The main reasons are the long time needed to detect an idle channel and inefficient ways of dealing with clock drift. This work introduces novel solutions to these problems, mainly at Layer 2 of the OSI model, that significantly reduce idle listening. First, nodes predict future drift and reduce the time needed to compensate clock uncertainty among neighbors. Second, they quickly detect an idle channel and power down the transceiver. In some scenarios, nodes work 30\% longer owing to these solutions. To tackle problems with unreliable wireless links, sensor nodes may apply various solutions at Layer 2. For example, with Automatic Repeat reQuest (ARQ) protocol they send retries on frame losses, resulting in extra energy consumption. This work examines the impact of ARQ on the lifetime and on the reception rate. Several indoor and outdoor experiments showed that with only 1-2 retries nodes can handle many communication problems. Besides, owing to the idle-listening reduction, mentioned previously, ARQ shortens the lifetime by 10\% only. Although this work addresses particular applications, the solutions presented here can be used in other scenarios and with different protocols. For instance, the energy-efficient drift compensation approach can be directly used in any schedule-based MAC protocols, like the one based on the IEEE 802.15.4 standard. Besides, any protocol can benefit from the solution to the idle-listening reduction based on the early detection of idle channel. Finally, owing to the analytical model that estimates the lifetime of nodes, researches and developers can early evaluate MAC protocols running on various hardware platforms.}, subject = {Rechnernetz; Drahtloses Sensorsystem; Verteiltes System; Kommunikationsprotokoll; Drahtlose Kommunikation; Sensornetze; Kurze Latenzen; Uhrendrift; Medienzugriff; Wireless communication; Sensor networks; Short delay; Clock drift; MAC}, language = {en} } @phdthesis{Dyka2013, author = {Dyka, Zoya}, title = {Analyse und Vorhersage des Fl{\"a}chen- und Energieverbrauches optimaler Hardware Polynom-Multiplizierer f{\"u}r GF(2ⁿ) f{\"u}r elliptische Kurven Kryptographie}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-27240}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {Die Anwendung asymmetrischer Kryptosysteme, z.B. elliptische Kurven Kryptographie (ECC), erfordert große Rechenkapazit{\"a}t die normalerweise auf von mobilen Ger{\"a}ten bzw. drahtlosen Sensorknoten nicht zur Verf{\"u}gung steht. Die Implementierung der ECC in Hardware reduziert den Zeit- und Energie-Aufwand. Die Optimierung der Hardware-Implementierungen dient nicht nur der weiteren Reduktion des Zeit- und Energieverbrauches sondern hilft dar{\"u}ber hinaus die Herstellungskosten zu verringern, so dass solche L{\"o}sungen auch f{\"u}r kosteng{\"u}nstige Ger{\"a}te einsetzbar werden. Im Rahmen dieser Dissertation wurden Optimierungsm{\"o}glichkeiten f{\"u}r die Multiplikation der Polynome, die f{\"u}r EC-Operationen eingesetzt werden, untersucht. Ziel der Optimierungen war, dass die Multiplikation mit einer minimalen Anzahl von Additionen (also XOR-Gattern) und Multiplikationen (also AND-Gattern) durchgef{\"u}hrt werden kann. Im Rahmen dieser Arbeit wurde die iterative Bearbeitung von 10 Multiplikations-Methoden (MM) im Gegensatz zur {\"u}blichen rekursiven Bearbeitung untersucht. Dabei wurde eine Reihenfolge der Operationen f{\"u}r jede der untersuchten MM ermittelt, die zu einer reduzierten Anzahl von XOR-Operationen f{\"u}hrt. Der Einsatz der optimierten Reihenfolge kann die Komplexit{\"a}t der MM wesentlich reduzieren. Zum Beispiel bei der generalisierten Karatsuba-MM [18] betr{\"a}gt die Reduktion des XOR-Aufwandes durchschnittlich 39 \% f{\"u}r Polynom-L{\"a}ngen bis 600 Bits. F{\"u}r die IHP 0,13μ-Technologie entspricht diese Reduktion des XOR-Aufwandes einer durchschnittlichen Fl{\"a}chen-Reduktion der Polynom-Multiplizierer um 35 \%. Bei der 4-Segment-Karatsuba-MM wird nicht nur der XOR-Aufwand, sondern auch die Signal-Verz{\"o}gerung im Vergleich zur rekursiven Anwendung der originalen Karatsuba-MM reduziert. Außerdem wurde ein Algorithmus zur Bestimmung einer fl{\"a}chen- und/oder energieoptimalen Kombination der Multiplikations-Methoden entwickelt. Mit dem vorgeschlagenen Algorithmus wurden die fl{\"a}chen- und die energie-optimalen Kombinationen der MM f{\"u}r Polynom-L{\"a}ngen bis 600 Bits bestimmt. Alle ECC-relevanten Polynom-L{\"a}ngen liegen in diesem Bereich. Die durchschnittliche Reduktion der Fl{\"a}chen im Vergleich zu den rekonstruierten Daten aus [30] betr{\"a}gt 12 \%. Zus{\"a}tzlich wurde ein energieoptimaler serieller Mehr-Takt-Multiplizierer f{\"u}r 233-Bits Polynome auf Basis Karatsuba-{\"a}hnlicher Multiplikations-Methoden entwickelt. Dieser Multiplizierer nutzt die Winograd-MM und basiert auf einen fl{\"a}chenoptimierten 78-Bits-Teil-Multiplizierer. Die theoretischen Ergebnisse wurden mit Hilfe von Synthesedaten f{\"u}r die IHP Technologie erfolgreich verifiziert. Der Energieverbrauch und die Ausf{\"u}hrungszeit des Designs sind um 24 \% bzw. 28 \% kleiner als die des Vergleichsdesigns aus [28].}, subject = {Hardwareentwurf; Kryptologie; Elliptische Kurven Kryptographie; GF(2ⁿ); Polynom-Multiplikation; Optimierung; Hardware Implementierung; Elliptic curve cryptography; GF(2ⁿ); Polynomial multiplication; Optimization; Hardware implementation}, language = {de} } @techreport{BockDyka2015, author = {Bock, Estuardo Alpirez and Dyka, Zoya}, title = {Vulnerability assessment of an IHP ECC implementation}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-34908}, year = {2015}, abstract = {Mathematically, cryptographic approaches are secure. This means that the time an attacker needs for finding the secret by brute forcing these approaches is about the time of the existence of our world. Practically, an algorithm implemented in hardware is a device that generates a lot of additional data during calculation. Its power consumption, electromagnetic radiation etc. can be measured, saved and analysed for the key extraction. Such attacks - the side channel analysis attacks (SCA attacks) - are significant threats when applying cryptographic algorithms. By taking the issue of physical attacks into consideration when implementing a cryptographic algorithm, it is possible to design an implementation that is resilient - at least to a certain extend - against side channel analyses. In this report, we give implementation details of the IHP accelerator for the elliptic curve point multiplication. We analysed the implemented algorithm ow and its power consumption using simulated power traces for the 130nm CMOS IHP technology. We made a horizontal power analysis attack using the difference-of-means test with the goal of finding potential SCA leakage sources, i.e. finding the operations in the algorithmic ow that are responsible for the correct extraction of the cryptographic key.}, subject = {Elliptic curve cryptography; Side channel analysis; Power analysis; Difference of means test; Hardware; CMOS-Schaltung; Kryptologie}, language = {en} }