@phdthesis{Wang2008, author = {Wang, Li}, title = {Millimeter-wave Integrated Circuits in SiGe:C Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-5993}, school = {BTU Cottbus - Senftenberg}, year = {2008}, abstract = {During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.}, subject = {Integrierte Mikrowellenschaltung; Silicium; Germanium; MMiC; Integrierte Millimeterwellenschaltung; Millimeter-wave; IC; SiGe; HBT; W-band}, language = {en} } @phdthesis{Borokhovych2011, author = {Borokhovych, Yevgen}, title = {High-speed data capturing components for Super Resolution Maximum Length Binary Sequence UWB Radar}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-24501}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {Within framework of UKoLoS project the new Super Resolution Maximum Length Binary Sequence UWB Radar (M-sequence radar) was developed. The radar consists of an M-sequence generator, transmitter front-end, receiver front-end, data capturing device and data processing blocks, whose design responsibilities were carried out by four institutions. In this thesis the design and measurements of the data capturing device components is described. Logically the data capturing device can be divided into three parts; a capturing part, realized with the high-speed analog-to-digital converter, a predictor, realized with the high-speed digital-to-analog converter and a subtraction amplifier, which in this particular work is integrated into the receiver front-end. The main challenge of the work is to implement the A/D converter, which works at full speed of the radar. Despite the radar architecture allows capturing data with undersampling, it leads to waste of transmitted energy. Therefore the ADC has to capture reflected signal with the full system clock rate of 10 GHz and should have a full Nyquist 5 GHz effective resolution bandwidth. Implementation of the conventional 4-bit full flash ADC with specified bandwidth is not possible in the IHP SiGe BiCMOS technology because some critical blocks, namely the reference network, can not achieve 5 GHz effective resolution bandwidth. To overcome this problem a new configuration of the differential reference network is proposed. The new reference network has a segmented, free configurable architecture. As extreme case it can be realized as a full parallel network and in such configuration the maximal bandwidth can be achieved. The proposed network was implemented in the A/D converter and measured. The bandwidth of the ADC with new network is several times higher than the bandwidth of the conventional ADC,while keeping power dissipation the same. Further the proposed network has possibility to equalize the bandwidth in each output node and in that way optimize overall power dissipation. The other advantage is the possibility of electronic calibration of separate voltage shift in the network. The second component of the data capturing device is the D/A converter, which is required to have the accuracy which corresponds to full accuracy of the data capturing device, better than 0.2\% in our case. Measurements showed that error due to mismatch of the components was 10 times higher than required. To meet the accuracy specification an external off-line calibration of the DAC was implemented. Using calibration the predictor errors less than 0.15\% were achieved.}, subject = {Analog-Digital-Umsetzer; Digital-Analog-Umsetzer; Analog-Digital-Wandler; Digital-Analog-Wandler; Folge-HalteVerst{\"a}rker; M-Sequenz UWB-Radar; Analog-to-digital converter; Full flash; Track-and-hold amplifier; Reference network}, language = {en} } @phdthesis{Sun2009, author = {Sun, Yaoming}, title = {Design of an integrated 60 GHz Transceiver Front-End in SiGe:C BiCMOS Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-11384}, school = {BTU Cottbus - Senftenberg}, year = {2009}, abstract = {This thesis describes the complete design of a low cost 60 GHz front end in SiGe BiCMOS technology. It covers the topics of a system plan, designs of building blocks, designs of application boards and real environment tests. Different LNA and mixer topologies have been investigated and fabricated. Good agreements between measurements and simulations have been achieved by using the self-developed component models. A transceiver front end system is built based on these blocks. A heterodyne architecture with a 5 GHz IF is adopted because it is compatible with the standard IEEE 802.11a, which allows the reuse of some existing building blocks of the 5 GHz transceiver. The transceiver chips are assembled onto application boards and connected by bond-wires. Bond-wire inductances have been minimized by using a cavity and compensated by an on board structure. The front end has been tested by both QPSK and OFDM signals in an indoor environment. Clear constellations have been measured. This was the first silicon based 60 GHz demonstrator in Europe and the second in the world.}, subject = {MMIC; Hochfrequenzschaltung; Transceiver; 60-GHz-Transceiver; MMIC; Integrierte Hochfrequenzschaltungen; Einchip-L{\"o}sung; Drahtlose Kommunikation; 60 GHz transceiver; MMIC; RFIC; Single chip solution; Wireless communication}, language = {en} } @phdthesis{Piz2011, author = {Piz, Maxim}, title = {Wideband OFDM System for Indoor Communication at 60 GHz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-22909}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {The license-free 60 GHz band enables a new breed of wireless networks offering data rates in the range of one to a few Gigabit per second over short distances. This thesis investigates the performance of a 60 GHz system using coded OFDM modulation and directive antennas for the transmitter and receiver. The study includes the impact of the 60 GHz propagation channel, impairments of a frontend in Si-Ge technology and considerations with respect to an efficient implementation. A major part of the work consists in the specification of a physical layer, which is optimized for the given wireless link and enables an implementation with programmable logic devices at moderate clock speed. For the selection of a channel code, the performance of two coding schemes is compared for the 60 GHz channel. The first scheme consists of a standard convolutional code and an outer Reed-Solomon code, whereas the second scheme is made up of an LDPC code with similar complexity. The interleaving scheme for the convolutional code is optimized to yield best performance. Furthermore, algorithms are developed and simulated for all essential system components of the OFDM receiver. The implementation of these components is also considered. A new synchronization scheme is introduced, which offers a high degree of robustness at low complexity. In this scheme, the fine timing synchronization shares the same hardware resources as the channel estimator. This approach results in a significant reduction of chip area. A new tracking algorithm is developed, which adequately compensates for the fluctuations of carrier phase, timing and channel impulse response. Finally, the implementation of the FFT and Viterbi decoder is discussed. The system architecture of the receiver requires a high degree of parallel processing and uses a deep processing pipeline to keep the clock frequency low. It is shown how to combine the system components into an efficient system under these conditions. The performance of the complete system is investigated for the static and time-variant channel. It is shown that despite the low complexity and high latency, the system achieves good performance. The baseband processor has been realized as a narrowband version with 400 MHz channels and broadband version with 2 GHz channels and improved algorithms. This has been done on an FPGA platform.}, subject = {Drahtloses lokales Netz; OFDM; OFDM; 60 GHz Kommunikation; WPAN; WLAN; Basisband Design; OFDM; 60 GHz Communication; WPAN; WLAN; Baseband Design}, language = {en} } @phdthesis{Peter2011, author = {Peter, Steffen}, title = {Tool-supported development of secure wireless sensor networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-24671}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {The development of secure systems is already a very challenging task. In the domain of wireless sensor networks this challenge is even aggravated by severe constraints of the sensor node devices and the exposed character of the networks. To cope with this issue, this thesis proposes a tool-supported development flow named configKIT, that helps users to integrate secured applications in the domain of Wireless Sensor Networks. It is a component-based framework that selects and composes configurations of hardware and software components for WSN applications from high-level user requirements, automatically. Therefore, the composition process utilizes a flexible meta-model to describe properties of the components, the requirements, and the system semantics, which allows the assessment of the behavior of the composed system. Based on this modeling technology five practical security models are investigated, which base on different technical views on a general security ontology for WSNs. Each model is discussed theoretically and practically, based on a practical integration in the configKIT framework. The configuration toolkit and the security models are finally evaluated by applying the techniques developed to the non-trivial example of secure in-network aggregation. The evaluation shows that all five practical security models developed in this thesis work correctly and with reasonable model overhead. These results promote the notion of a practically applicable toolkit to configure secure applications in WSNs.}, subject = {Drahtloses Sensorsystem; Drahtlose Sensor Netzwerke; Sicherheit; Konfiguration; Wireless Sensor Networks; Security; Configuration}, language = {en} } @phdthesis{Ehrig2014, author = {Ehrig, Marcus}, title = {Hardwareimplementierte latenzarme drahtlose Medienzugriffsprotokolle f{\"u}r h{\"o}chsten Datendurchsatz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-34828}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Der Fortschritt der Technik erm{\"o}glicht immer leistungsf{\"a}higere drahtlose Dienste mit hohen Anforderungen an Latenz, Jitter und {\"U}bertragungsgeschwindigkeit. Aktuelle digitale Protokolle f{\"u}r drahtgebundene hochaufl{\"o}sende Multimedia{\"u}bertragungen (HDMI, DisplayPort) oder Peripherieschnittstellen (USB, PCIe, SATA) in der Computertechnik erreichen Datenraten im Multi-Gigabit Bereich. Die {\"U}bertragung der Inhalte z.B. Filme, Musikstreaming oder Datei{\"u}bertragungen mit Hilfe breitbandiger drahtloser {\"U}bertragungsverfahren vereinfacht die kabellose „Installation" und die daraus folgende Benutzerfreundlichkeit (Mobilit{\"a}t) im Heimbereich (Indoor). Weiterhin werden Systeme mit hohen Datenraten und kleinen Latenzen unter 5 ms im Mobilfunkbereich ben{\"o}tigt, um Basisstationen (3G, LTE) mit dem Kernnetzwerk zu verbinden. Diese Backhaul-Verbindungen k{\"o}nnen auch im innerst{\"a}dtischen Bereich zum Aufbau von Small-Cell-Installationen genutzt werden, da nicht immer eine Kabelverlegung m{\"o}glich ist. Eine Verkettung der Verbindungen vergr{\"o}ßert den Abstand zum Zugangspunkt des Kernnetzes und stellt zus{\"a}tzliche Anschlußpunkte f{\"u}r Basisstationen bereit. Allerdings vergr{\"o}ßert sich auch die Latenz f{\"u}r die weiter entfernten Stationen. In dieser Arbeit wird ein MAC-Protokoll f{\"u}r hochratige und latenzarme drahtlose Verbindungen vorgestellt. Dazu werden sowohl Punkt-zu-Punkt- als auch Punkt-zu-Mehrpunkt-Verbindungen auf ihre speziellen Anforderungen bei der Implementierung der MAC-Komponenten in einer programmierbaren Hardware (FPGA) analysiert. Eine Integration des MAC-Protokolls zusammen mit einem OFDM-Basisbandprozessor mit Brutto-Datenraten gr{\"o}ßer 5 GBit/s erlaubt die {\"U}berpr{\"u}fung der Funktionalit{\"a}t sowie die Messung wichtiger Protokollparameter unter realen Einsatzbedingungen. Das vorgeschlagene Medienzugriffsprotokoll unterst{\"u}tzt den Einsatz von Beamsteering-Verfahren zur Suche von benachbarten Kommunikationsteilnehmern und den gleichzeitigen r{\"a}umlich getrennten Kanalzugriff mehrerer Kommunikationsteilnehmer. Eine Anwendungsschnittstelle f{\"u}r nutzerspezifische Implementierungen mit exklusivem Zugriff auf das {\"U}bertragungsmedium erleichtert die Integration zus{\"a}tzlicher Funktionalit{\"a}t wie z.B. eine hochaufl{\"o}sende Entfernungsmessung. Weiterhin wird ein Verfahren zur latenzarmen Detektierung und Umschaltung blockierter Pfade vorgestellt. Umfangreiche Simulationen best{\"a}tigen die Funktionalit{\"a}t des MAC-Protokolls in unterschiedlichen Szenarien mit und ohne {\"U}bertragungsfehler.}, subject = {Drahtlose Breitbandkommunikation; Drahtlose Medienzugriffssteuerung (MAC); Hochdirektive Antennen; Wireless Broadband Communication; Highly Directional Antennas; Breitbandkommunikation; Breitbandantenne; Funktechnik; Zugangsverfahren}, language = {de} } @phdthesis{Piotrowski2011, author = {Piotrowski, Krzysztof}, title = {Assessment of the feasibility of distributed shared memory and data consistency for wireless sensor networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-23718}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {Wireless sensor networks (WSNs) are built of cheap, resource constraint devices, capable to collect process and communicate data. WSN applications depend on the data they collect. In other words, the applications require the data to be available, even if some WSN nodes fail. The challenge is that nodes are prone to fail and todays WSNs do not provide highly reliable data storage. Thus, the quality of the service provided by the system, regarding the data handling, is one of the most important factors. Data replication increases the availability of the data and thus, the robustness and quality of the data storage. But the existence of several copies of data items in the WSN induces the data consistency to become of high importance in order to ensure proper behavior of the application. This work investigates the feasibility of data consistency models used in distributed shared memory in WSNs to provide more powerful distributed systems with reliable data exchange. As a starting point WSNs and consistency approaches are introduced. Based on those basics, the mechanisms needed to allow for data consistency are discussed as a theoretical framework for the prototypical implementation of a data consistency providing middleware, which was implemented as part of this work. The middleware adapts the mechanisms known from original memory consistency approaches to be usable in the sensor network area and proposes own, low cost mechanisms, as well. The latter are at least partially based on the idea that within the shared memory of WSNs information is the major concern and that by that the replica update rates can be tailored to the application. In order to allow for ease of use of the middleware the replication schemes and consistency mechanisms can be defined by the application engineer as a policy. The latter is transformed and injected into the middleware code by a pre-compiler, so that the application engineer no longer needs to implement replication and consistency mechanisms herself. The most appropriate memory consistency models are implemented and evaluated using the framework proposed in this thesis.}, subject = {Verteiltes System; Drahtloses Sensorsystem; Verteilter gemeinsamer Speicher; Drahtlose Sensornetze; Datenkonsistenz; Distributed shared memory; Wireless sensor networks; Data consistency}, language = {en} } @phdthesis{Simevski2014, author = {Simevski, Aleksandar}, title = {Architectural framework for dynamically adaptable multiprocessors regarding aging, fault tolerance, performance and power consumption}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-32572}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Despite the numerous benefits that Integrated Circuit (IC) technology downscaling brings, it also introduces many challenges. First of all, IC dependability is lowering: both lifetime reliability and resilience to single event effects is decreasing. Another major problem is the increased power consumption. On the other hand, the vast available space enables integrating hundreds of processor cores in a single chip! Multiprocessing is for over a decade the main architectural trend because of two reasons. Firstly, the performance of single processors gained by architectural innovations reached the upper limit i.e., the point of diminishing returns. Secondly, the operating frequency could not be increased due to the excessive power consumption, as pointed out. This work proposes a multiprocessor architectural framework that addresses many challenges related to dependability, power consumption and performance. The key idea is dynamical adaptation to the application requirements of fault tolerance and performance, which is possibly done at the lowest rates of aging and power dissipation. The application may select one of the three basic operating modes: de-stress, fault-tolerant and high-performance. De-stress mode prolongs multiprocessor lifetime and reduces power consumption by using core gating patterns that systematically power- or clock-off entire cores in the multiprocessor. These patterns use the information supplied by novel IC aging monitors. Fault-tolerant mode, on the other hand, increases error resilience by forming core-level NMR (N-modular redundant) systems using the multiprocessor cores. That is, entire cores are tightly synchronized to execute the same task simultaneously. Voting is done on each clock cycle using special, programmable NMR voters. Core-level NMR enables masking faults without invoking recovery procedures which is appreciated by timing-critical, or, real-time applications. Finally, high-performance mode is used for boosting multiprocessor performance. The framework is evaluated using a novel environment for automated fault injection, as well as a novel multiprocessor verification platform. A vast number of experiments were made which led to closed-form expressions that determine the number of cores N required to survive the projected mission time, given the fault rate. Moreover, a newly-developed method for lifetime evaluation based on the Weibul distribution shows the benefits of using core gating patterns. E.g., the new Youngest-First Round-Robin (YFRR) pattern enables up to 31\% increase in system's lifetime compared to a simple Round-Robin.}, subject = {Dependable multiprocessor; Multiprocessor lifetime; Multiprocessor fault tolerance; Zuverl{\"a}ssige Multiprozessoren; Multiprozessoren Alterung; Mehrprozessorsystem; Fehlertoleranz; Fehlererkennung}, language = {en} } @phdthesis{Hund2012, author = {Hund, Johannes}, title = {Entwurf eines robusten drahtlosen Kommunikationssystems f{\"u}r die industrielle Automatisierung unter harten Echtzeitbedingungen auf Basis von Ultrawideband-Impulsfunk}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-25219}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {Ziel dieser Dissertation war es, die Eignung von Ultra-Breitband-Pulsfunk (IR-UWB) f{\"u}r die drahtlose Kommunikation in der Sensor/Aktor-Ebene der Fertigungsautomatisierung zu untersuchen. Dazu wurde ein drahtloses Kommunikationssystem auf Basis standardisierter Protokolle entworfen und untersucht. Diese Anwendung erfordert die Erf{\"u}llung harter Echtzeitf{\"a}higkeit im Bereich weniger Millisekunden in industriellen Umgebungen. Ein solches Umfeld stellt aufgrund eines hohen Rauschpegels und vieler metallischer Oberfl{\"a}chen, die Multipfad-Effekte verursachen, sehr hohe Anspr{\"u}che an das Latenzverhalten und die Robustheit. Deshalb waren die Hauptziele die Reduzierung von Latenz und gleichzeitige Erh{\"o}hung der Robustheit f{\"u}r den existierenden, auf IR-UWB basierenden Standard IEEE 802.15.4a. Dieser Standard ist unter anderem deshalb vielversprechend, da er sich mit sehr preisg{\"u}nstigen, nicht-koh{\"a}renten Empf{\"a}ngern von geringer Komplexit{\"a}t umsetzen l{\"a}sst, die trotzdem relativ robust gegen{\"u}ber Multipfad-Effekten sind. Es wurde gezeigt, dass sich auch mit diesen g{\"u}nstigen Ger{\"a}ten durch Optimierung des Standards eine hohe {\"u}bertragungssicherheit bei geringer Latenz realisieren l{\"a}sst. Es wurden Modifikationen zur Optimierung der Robustheit und Latenz des bisher {\"u}blichen Designs von nicht-koh{\"a}renten IR-UWB-Empf{\"a}ngern vorgestellt. Durch Erg{\"a}nzungen zu der im Standard beschriebenen Modulation und Kodierung konnte die Verl{\"a}sslichkeit zus{\"a}tzlich gesteigert werden. Um diese optimierte PHY-Schicht effizient einsetzen zu k{\"o}nnen, wurde eine spezialisierte MAC-Schicht f{\"u}r die Automatisierung, die in einem Entwurf f{\"u}r den kommenden Standard IEEE 802.15.4e beschrieben wird, eingesetzt. Da bei dieser MAC-Schicht die Kommunikationsmuster im Voraus bekannt sind, war weitere schicht{\"u}bergreifende, applikations-spezifische Optimierung m{\"o}glich, die eine weitere Reduzierung der Latenz sowie eine Erh{\"o}hung der Robustheit erbrachte. Im Zuge der Arbeit wurde ein flexibel konfigurierbarer Simulator f{\"u}r IR-UWB auf Basis von industriell akzeptierten Kanalmodellen erstellt. Dieser Simulator wurde auch zur Evaluation und Verifikation der Forschungsergebnisse benutzt. Das entworfene Gesamtsystem ist {\"u}ber mehrere Parameter konfigurierbar und dadurch an weitere Anwendungen in der Automatisierung anpassbar. Eine dieser Konfigurationen wurde durch Simulation evaluiert. Sie zeigt mindestens die gleiche und zum Teil bessere Performance als bisherige drahtlose oder drahtgebundene L{\"o}sungen f{\"u}r die Sensor/Aktor-Ebene der Fertigungsautomatisierung, wie z.B. AS-Interface, Bluetooth I/O oder WISA. F{\"u}r den repr{\"a}sentativen Fall von 32 Teilnehmern mit jeweils einem Byte Prozessdaten erreicht sie eine Zykluszeit von 1,88 ms. Damit kann eine eine mittlere Reaktionszeit von 985 µs erreicht werden und eine harte Echtzeitschranke von 15 ms mit einer Fehlerwahrscheinlichkeit unter 10^-9 eingehalten werden. Das Kommunikationssystem wurde auch in Hardware auf FPGA-Basis implementiert. Da das benutzte analoge Front-End, ein fr{\"u}her Prototyp eines IEEE 802.15.4a-kompatiblen Front-Ends, noch keine repr{\"a}sentativen Messungen zuließ, wurde die Funktion durch eine Basisbandverbindung {\"u}ber Kabel verifiziert.}, subject = {Drahtloses lokales Netz; Ultraweitband; Breitband{\"u}bertragung; Echtzeitverarbeitung; UWB; Automatisierung; Echtzeit; Impulsfunk; IEEE 802.15.4a; UWB; Automation; Real-time; Impulse radio; IEEE 802.15.4a}, language = {de} } @phdthesis{Panić2014, author = {Panić, Goran}, title = {A methodology for designing low power sensor node hardware systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-33376}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {The design of embedded sensor node hardware systems is a challenging task driven by the increasing demands for low power, high efficiency, low cost and small size. These unique requirements make the usage of off-the-shelf general purpose microcontrollers fairly inefficient. For many wireless sensor network applications, the design of a dedicated low power sensor node microcontroller is the only way to answer specific application requirements. According to the trends in device, process and design technology, the development of sensor node devices is relying on a cheap planar bulk-CMOS technology, where power consumption is dominated by static power loss caused by high leakage currents. To keep the power at acceptable level, designers are compelled to apply the methodologies based on advanced low power techniques that target both static and dynamic power in the chip. The decisions made early in design phase are likely to determine the energy efficiency of the final design. Therefore, the choice of power saving strategy is the key challenge in designing energy-efficient sensor node hardware. This work presents a methodology that assists designers meeting the critical design decisions regarding power, early in the design process. The presented methodology extracts the activity profiles of single system components and applies them in the developed models for energy estimation of particular low power implementation. The energy estimation models account for the energy overhead introduced by specific low power techniques, enabling comprehensive exploration of system's energy efficiency in a given application scenario. Special attention is paid to the methodology utilization in typical wireless sensor network applications. Accordingly, the examples of activity profiling in wireless sensor node systems are presented. The proposed methodology is integrated within a power-driven design flow and applied to the design of an embedded sensor node microcontroller. This methodology is used to perform the cross comparison of alternative low power implementations for the target system architecture. The implementation relying on concurrent clock and power gating is selected as the most energy efficient and consequently realised. Power switching cells and power control logic have been designed and characterized. Also, the final system architecture, basic system components and applied design process are described. Finally, the developed power-gated sensor node microcontroller is implemented, fabricated and successfully tested. The chip measurements results are presented and analyzed. The analysis of different low power approaches applied to the target system architecture has shown large impact of clock gating on the system energy. In a given application scenario, the clock gating implementation has reduced 72 times the dynamic energy and 12 times the total energy of the system. The implementation of power gating technique has gained 2.8 times reduction of the leakage energy and 2 times reduction of the total system energy compared to the clock gating only implementation. The analysis of two alternative power gating approaches has emphasized the significance of partitioning in power-gated design. A heuristic partitioning that combines two specific blocks having successive activity phases into a single power domain, thereby reducing design complexity and chip area, has been shown to have positive impact on the energy efficiency of the target design.}, subject = {Wireless sensor networks; Sensor node; Low power design; Power gating; ASIC; Drahtlose Sensornetze; Sensorknoten; Energieeffizientes Design; Stromspartechniken; Chipdesign; Drahtloses Sensorsystem; Mikroprozessor; Eingebettetes System}, language = {en} } @phdthesis{Petri2012, author = {Petri, Markus}, title = {Latenzverringerung in Basisbandprozessoren am Beispiel eines hochratigen OFDM-Kommunikationssystems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-26674}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {In modernen digitalen {\"U}bertragungssystemen ist der gesamte Datendurchsatz nicht mehr allein durch die Datenrate - z. B. aufgrund der begrenzten Bandbreite - eingeschr{\"a}nkt. Stattdessen haben die bei der Verarbeitung entstehenden Latenzen einen immer gr{\"o}ßeren Einfluss auf die erzielbare Systemperformance. In der Fachliteratur beschriebene Untersuchungen zur Latenzverringerung in digitalen Basisbandprozessoren beschr{\"a}nken sich meist auf die Optimierung eigenst{\"a}ndiger Module. Im Rahmen dieser Arbeit werden, basierend auf einer Untersuchung der Basisbandmodule auf ihren Latenzbeitrag und einer Darstellung der Latenzauswirkungen, bestehende Verfahren der Latenzverringerung evaluiert und neue Verfahren zur Latenzreduktion entworfen. Die praktischen Auswirkungen werden dabei anhand der Latenzmodellierung eines bestehenden 60 GHz-OFDM-Kommunikationssystems aufgezeigt. Die zur Anwendung der neu entworfenen Verfahren notwendigen strukturellen {\"A}nderungen in der Basisbandverarbeitung werden detailliert dargestellt. Weiterhin wird eine allgemeine Methodik des latenzarmen Systementwurfs vorgestellt, die die Anwendung der neu entworfenen Verfahren beinhaltet. Bei der Darstellung von Verfahren zur Latenzverringerung liegt der Schwerpunkt auf der zur Durchsatzsteigerung {\"u}blicherweise verwendeten, aber noch nicht im Zusammenhang mit der Latenzverringerung beschriebenen Anwendung von parallelen Datenverarbeitungsstrukturen sowie auf der neu vorgeschlagenen Anwendung von Spekulation. Mithilfe der spekulativen Demodulation und der spekulativen Dekodierung lassen sich Latenzen aufgrund von Abh{\"a}ngigkeiten in der Datenverarbeitung einfach vermeiden. Die sich aus den spekulativen Verfahren ergebenden Auswirkungen auf die MAC-Ebene werden zum Schluss kurz diskutiert.}, subject = {OFDM; Basisband; Latenzzeit ; Latenzverringerung; Basisbandprozessor; OFDM; Spekulative Verarbeitung; Parallelverarbeitung; Latency reduction; Baseband processor; OFDM; Speculative processing; Parallel processing}, language = {de} }