@phdthesis{Hund2012, author = {Hund, Johannes}, title = {Entwurf eines robusten drahtlosen Kommunikationssystems f{\"u}r die industrielle Automatisierung unter harten Echtzeitbedingungen auf Basis von Ultrawideband-Impulsfunk}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-25219}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {Ziel dieser Dissertation war es, die Eignung von Ultra-Breitband-Pulsfunk (IR-UWB) f{\"u}r die drahtlose Kommunikation in der Sensor/Aktor-Ebene der Fertigungsautomatisierung zu untersuchen. Dazu wurde ein drahtloses Kommunikationssystem auf Basis standardisierter Protokolle entworfen und untersucht. Diese Anwendung erfordert die Erf{\"u}llung harter Echtzeitf{\"a}higkeit im Bereich weniger Millisekunden in industriellen Umgebungen. Ein solches Umfeld stellt aufgrund eines hohen Rauschpegels und vieler metallischer Oberfl{\"a}chen, die Multipfad-Effekte verursachen, sehr hohe Anspr{\"u}che an das Latenzverhalten und die Robustheit. Deshalb waren die Hauptziele die Reduzierung von Latenz und gleichzeitige Erh{\"o}hung der Robustheit f{\"u}r den existierenden, auf IR-UWB basierenden Standard IEEE 802.15.4a. Dieser Standard ist unter anderem deshalb vielversprechend, da er sich mit sehr preisg{\"u}nstigen, nicht-koh{\"a}renten Empf{\"a}ngern von geringer Komplexit{\"a}t umsetzen l{\"a}sst, die trotzdem relativ robust gegen{\"u}ber Multipfad-Effekten sind. Es wurde gezeigt, dass sich auch mit diesen g{\"u}nstigen Ger{\"a}ten durch Optimierung des Standards eine hohe {\"u}bertragungssicherheit bei geringer Latenz realisieren l{\"a}sst. Es wurden Modifikationen zur Optimierung der Robustheit und Latenz des bisher {\"u}blichen Designs von nicht-koh{\"a}renten IR-UWB-Empf{\"a}ngern vorgestellt. Durch Erg{\"a}nzungen zu der im Standard beschriebenen Modulation und Kodierung konnte die Verl{\"a}sslichkeit zus{\"a}tzlich gesteigert werden. Um diese optimierte PHY-Schicht effizient einsetzen zu k{\"o}nnen, wurde eine spezialisierte MAC-Schicht f{\"u}r die Automatisierung, die in einem Entwurf f{\"u}r den kommenden Standard IEEE 802.15.4e beschrieben wird, eingesetzt. Da bei dieser MAC-Schicht die Kommunikationsmuster im Voraus bekannt sind, war weitere schicht{\"u}bergreifende, applikations-spezifische Optimierung m{\"o}glich, die eine weitere Reduzierung der Latenz sowie eine Erh{\"o}hung der Robustheit erbrachte. Im Zuge der Arbeit wurde ein flexibel konfigurierbarer Simulator f{\"u}r IR-UWB auf Basis von industriell akzeptierten Kanalmodellen erstellt. Dieser Simulator wurde auch zur Evaluation und Verifikation der Forschungsergebnisse benutzt. Das entworfene Gesamtsystem ist {\"u}ber mehrere Parameter konfigurierbar und dadurch an weitere Anwendungen in der Automatisierung anpassbar. Eine dieser Konfigurationen wurde durch Simulation evaluiert. Sie zeigt mindestens die gleiche und zum Teil bessere Performance als bisherige drahtlose oder drahtgebundene L{\"o}sungen f{\"u}r die Sensor/Aktor-Ebene der Fertigungsautomatisierung, wie z.B. AS-Interface, Bluetooth I/O oder WISA. F{\"u}r den repr{\"a}sentativen Fall von 32 Teilnehmern mit jeweils einem Byte Prozessdaten erreicht sie eine Zykluszeit von 1,88 ms. Damit kann eine eine mittlere Reaktionszeit von 985 µs erreicht werden und eine harte Echtzeitschranke von 15 ms mit einer Fehlerwahrscheinlichkeit unter 10^-9 eingehalten werden. Das Kommunikationssystem wurde auch in Hardware auf FPGA-Basis implementiert. Da das benutzte analoge Front-End, ein fr{\"u}her Prototyp eines IEEE 802.15.4a-kompatiblen Front-Ends, noch keine repr{\"a}sentativen Messungen zuließ, wurde die Funktion durch eine Basisbandverbindung {\"u}ber Kabel verifiziert.}, subject = {Drahtloses lokales Netz; Ultraweitband; Breitband{\"u}bertragung; Echtzeitverarbeitung; UWB; Automatisierung; Echtzeit; Impulsfunk; IEEE 802.15.4a; UWB; Automation; Real-time; Impulse radio; IEEE 802.15.4a}, language = {de} } @phdthesis{Krstic2006, author = {Krstic, Milos}, title = {Request-driven GALS technique for datapath architectures}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-000000888}, school = {BTU Cottbus - Senftenberg}, year = {2006}, abstract = {In this thesis a novel Globally Asynchronous Locally Synchronous (GALS) technique applicable to wireless communication systems and generally to datapath architectures is presented. The proposed concept is intended for point-to-point communication with very intensive but bursty data transfer. This concept is based on a request-driven operation of locally synchronous modules. The key idea is that a module can use the input request signal as its clock while receiving a burst of data. The developed GALS technique is applied to the design of an IEEE 802.11a compliant baseband processor with the aim to alleviate the problems of system integration, power consumption and electro-magnetic interference. The GALS design was compared with a synchronous version of the baseband processor. In our experimental setup we have measured a 1\% reduction in dynamic power consumption, 30\% reduction in instantaneous supply voltage variations, and 5 dB reduction in spectral noise.}, subject = {GAL ; GALS; Systemintegration; Asynchroner Entwurf; EMI; BIST}, language = {en} } @phdthesis{Zeidler2013, author = {Zeidler, Steffen}, title = {Enabling functional tests of asynchronous circuits using a test processor solution}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29643}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {During the last years, the asynchronous design style has been rediscovered as a potential solution to upcoming design issues in deep-submicron technologies. However, besides the lack of commercial tools supporting this design style, one major challenge is the test of asynchronous designs. Especially their event-driven behavior leads to problems during test. Basically, the timing of asynchronous circuits is determined by gate and wire delays that are sensitive to variations of environmental parameters (process, voltage and temperature). This leads to uncertainties in the timing of the responses. Consequently, standard commercial test systems cannot be used, because such systems read the responses at specific cycles and, therefore, could reject fault-free devices. Furthermore, available hardware testers are, in principle, not designed to react to signal events from the design-under-test as it is necessary to establish asynchronous communication via handshake signalling. As a result, even simple functional tests that only apply stimuli and read the responses of the design-under-test cannot be realized without preparatory measures. This work addresses these issues and proposes a concept to enable functional tests of asynchronous designs. The concept is based on a special test processor that provides generic interfaces used to establish asynchronous handshake communication with a device-under-test. By this, elastic functional tests can be realized that overcome the static timing of conventional tests and emulate the real operating environment of the design. Apart from the generic test processor architecture, an essential part of the concept deals with the establishment of the processor as a stand alone or embedded test equipment. A workflow is provided that describes how the device-under-test can be embedded into the test processor environment for performing the tests. Besides the interconnection between the asynchronous design and the test processor, this especially includes the generation of programs that realize the functional tests of the design. A methodology is introduced that generates the desired programs for the processor from a standard functional simulation of the design-under-test. Based on the generic concept, a framework including both a test processor implementation and the realization of the program generation is delivered. In order to evaluate the entire concept, this framework has been applied to functionally test an asynchronous arithmetic-logic-unit. In combination with additional experiments, conducted to determine the required resources, it has been shown that the introduced concept is a suitable approach to test asynchronous designs.}, subject = {Asynchrones Schaltwerk; Pr{\"u}ftechnik; Fehlererkennung; Asynchrone Schaltungen; Funktionaltest; Testprozessor; Transferprotokoll; Nichtdeterminismus; Asynchronous circuits; Functional test; Test processor; Transfer protocol; Nondeterminism}, language = {en} } @phdthesis{Piotrowski2011, author = {Piotrowski, Krzysztof}, title = {Assessment of the feasibility of distributed shared memory and data consistency for wireless sensor networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-23718}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {Wireless sensor networks (WSNs) are built of cheap, resource constraint devices, capable to collect process and communicate data. WSN applications depend on the data they collect. In other words, the applications require the data to be available, even if some WSN nodes fail. The challenge is that nodes are prone to fail and todays WSNs do not provide highly reliable data storage. Thus, the quality of the service provided by the system, regarding the data handling, is one of the most important factors. Data replication increases the availability of the data and thus, the robustness and quality of the data storage. But the existence of several copies of data items in the WSN induces the data consistency to become of high importance in order to ensure proper behavior of the application. This work investigates the feasibility of data consistency models used in distributed shared memory in WSNs to provide more powerful distributed systems with reliable data exchange. As a starting point WSNs and consistency approaches are introduced. Based on those basics, the mechanisms needed to allow for data consistency are discussed as a theoretical framework for the prototypical implementation of a data consistency providing middleware, which was implemented as part of this work. The middleware adapts the mechanisms known from original memory consistency approaches to be usable in the sensor network area and proposes own, low cost mechanisms, as well. The latter are at least partially based on the idea that within the shared memory of WSNs information is the major concern and that by that the replica update rates can be tailored to the application. In order to allow for ease of use of the middleware the replication schemes and consistency mechanisms can be defined by the application engineer as a policy. The latter is transformed and injected into the middleware code by a pre-compiler, so that the application engineer no longer needs to implement replication and consistency mechanisms herself. The most appropriate memory consistency models are implemented and evaluated using the framework proposed in this thesis.}, subject = {Verteiltes System; Drahtloses Sensorsystem; Verteilter gemeinsamer Speicher; Drahtlose Sensornetze; Datenkonsistenz; Distributed shared memory; Wireless sensor networks; Data consistency}, language = {en} } @phdthesis{Sun2009, author = {Sun, Yaoming}, title = {Design of an integrated 60 GHz Transceiver Front-End in SiGe:C BiCMOS Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-11384}, school = {BTU Cottbus - Senftenberg}, year = {2009}, abstract = {This thesis describes the complete design of a low cost 60 GHz front end in SiGe BiCMOS technology. It covers the topics of a system plan, designs of building blocks, designs of application boards and real environment tests. Different LNA and mixer topologies have been investigated and fabricated. Good agreements between measurements and simulations have been achieved by using the self-developed component models. A transceiver front end system is built based on these blocks. A heterodyne architecture with a 5 GHz IF is adopted because it is compatible with the standard IEEE 802.11a, which allows the reuse of some existing building blocks of the 5 GHz transceiver. The transceiver chips are assembled onto application boards and connected by bond-wires. Bond-wire inductances have been minimized by using a cavity and compensated by an on board structure. The front end has been tested by both QPSK and OFDM signals in an indoor environment. Clear constellations have been measured. This was the first silicon based 60 GHz demonstrator in Europe and the second in the world.}, subject = {MMIC; Hochfrequenzschaltung; Transceiver; 60-GHz-Transceiver; MMIC; Integrierte Hochfrequenzschaltungen; Einchip-L{\"o}sung; Drahtlose Kommunikation; 60 GHz transceiver; MMIC; RFIC; Single chip solution; Wireless communication}, language = {en} } @phdthesis{Piz2011, author = {Piz, Maxim}, title = {Wideband OFDM System for Indoor Communication at 60 GHz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-22909}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {The license-free 60 GHz band enables a new breed of wireless networks offering data rates in the range of one to a few Gigabit per second over short distances. This thesis investigates the performance of a 60 GHz system using coded OFDM modulation and directive antennas for the transmitter and receiver. The study includes the impact of the 60 GHz propagation channel, impairments of a frontend in Si-Ge technology and considerations with respect to an efficient implementation. A major part of the work consists in the specification of a physical layer, which is optimized for the given wireless link and enables an implementation with programmable logic devices at moderate clock speed. For the selection of a channel code, the performance of two coding schemes is compared for the 60 GHz channel. The first scheme consists of a standard convolutional code and an outer Reed-Solomon code, whereas the second scheme is made up of an LDPC code with similar complexity. The interleaving scheme for the convolutional code is optimized to yield best performance. Furthermore, algorithms are developed and simulated for all essential system components of the OFDM receiver. The implementation of these components is also considered. A new synchronization scheme is introduced, which offers a high degree of robustness at low complexity. In this scheme, the fine timing synchronization shares the same hardware resources as the channel estimator. This approach results in a significant reduction of chip area. A new tracking algorithm is developed, which adequately compensates for the fluctuations of carrier phase, timing and channel impulse response. Finally, the implementation of the FFT and Viterbi decoder is discussed. The system architecture of the receiver requires a high degree of parallel processing and uses a deep processing pipeline to keep the clock frequency low. It is shown how to combine the system components into an efficient system under these conditions. The performance of the complete system is investigated for the static and time-variant channel. It is shown that despite the low complexity and high latency, the system achieves good performance. The baseband processor has been realized as a narrowband version with 400 MHz channels and broadband version with 2 GHz channels and improved algorithms. This has been done on an FPGA platform.}, subject = {Drahtloses lokales Netz; OFDM; OFDM; 60 GHz Kommunikation; WPAN; WLAN; Basisband Design; OFDM; 60 GHz Communication; WPAN; WLAN; Baseband Design}, language = {en} } @phdthesis{Dietterle2009, author = {Dietterle, Daniel}, title = {Efficient protocol design flow for embedded systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-7848}, school = {BTU Cottbus - Senftenberg}, year = {2009}, abstract = {It is predicted that, in the next years, wireless sensor networks could be massively deployed in a wide variety of application areas, such as agriculture, logistics, automation, or infrastructure monitoring. An extremely low power consumption, high dependability, and low cost are common requirements for sensor nodes in all these applications. This can be achieved only by tiny, power-efficient microcontrollers and communication systems integrated on a single chip. Formal description techniques, such as SDL (Specification and Description Language), are suitable to formally prove properties of models designed in these languages. Code generators facilitate the automatic transformation of SDL models into software implementations, while preserving the properties of the model and, thus, achieving high system dependability. The implementations consist of the translated state machine behavior and, additionally, require a run-time environment for model execution. The objective of this work was to investigate an integrated design flow for embedded systems, which should allow the development of efficient and dependable system implementations from abstract SDL specifications. In this thesis, concepts for minimal SDL run-time environment have been devised and realized by an example implementation. Not only pure software implementations should be considered, but starting from these also the hardware/software (HW/SW) partitioning of the system should be supported. For this purpose, a cosimulation framework that allows the coupling of an instruction set simulator (ISS) with a functional SDL simulation has been investigated and prototypically implemented within the scope of this thesis. By shifting functionality to dedicated hardware components it is possible to take computational load from the microcontroller and to decrease the overall energy consumption by reducing the clock frequency and lowering the supply voltage. Due to the use of SDL, the design flow lends itself particularly to the implementation of communication protocols, and is limited to applications with soft real-time requirements. For an SDL-based design flow targeted to resource-constrained embedded systems, concepts and real implementations of minimal SDL run-time environments were lacking. Available software tools, indeed, enable the transformation of SDL models into C code, however for an efficient implementation, an integration into existing real-time operating systems (RTOS) for small microcontrollers is essential. A prototypical implementation of a run-time library for the Reflex RTOS has been created to validate our general concepts. It is about 30 \% faster and consumes less than half of the program memory compared to the operating system independent run-time environment of the tool vendor Telelogic. For simple SDL models, the application requires in total less than 8 kbytes program memory and 1 kbyte RAM. For the evaluation of design alternatives that realize different hardware/software partitionings, instruction set simulators are particularly suitable. They facilitate the identification of performance bottlenecks of the HW/SW system. Test stimuli are required in order to measure the performance and response time of systems under design. The development of an environment that generates such test signals can be a laborious task. Thus, it is reasonable, especially in the design of protocols, to use an SDL simulation of a communication network to generate these test stimuli. Such an SDL model already exists and is the basis for the implementation. The protocol implementation simulated by the ISS then becomes part of the network simulation. An efficient coupling of SDL simulations with instruction set simulators had to be investigated, and a solution is presented in this thesis. Based on the general concepts, a cosimulation framework for the ISS TSIM for the LEON2 processor was realized by the author. The joint SDL and instruction set simulation is very fast, which could be demonstrated by connecting a software implementation of the complex IEEE 802.15.3 medium access control (MAC) protocol with an SDL simulation of a network consisting of four devices. The real execution time for 10 seconds of simulation time amounted to just 50 seconds. The overall design flow was validated by means of a HW/SW implementation of the IEEE 802.15.3 wireless MAC protocol. The author designed a complete SDL model of the protocol and integrated it into Reflex. By using our cosimulation environment for the TSIM simulator, the model was partitioned into hardware and software. For the hardware part, a dedicated protocol accelerator was designed by the author. This hardware component was integrated on a single chip with the LEON2 processor and, finally, manufactured. It could be shown that the presented methodology enables the design and implementation of efficient HW/SW systems. Consequently, it can be applied to the development of dependable and energy-efficient wireless sensor nodes and other embedded systems.}, subject = {Eingebettetes System; Protocol Engineering; Cosimulation; IEEE 802.15.3; Model-based design; Protocol engineering; Cosimulation; IEEE 802.15.3}, language = {en} } @phdthesis{Ortmann2010, author = {Ortmann, Steffen}, title = {Definition and configuration of reliable event detection for application in wireless sensor networks}, isbn = {978-3-8322-9445-8}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-19602}, school = {BTU Cottbus - Senftenberg}, year = {2010}, abstract = {Ubiquitous systems based on wireless sensor networks will amazingly increase our quality of life. These systems are to be deployed in large areas with high density where hundreds or thousands of nodes are used. Certainly that demands to use low cost devices with limited resources, which in turn are prone to faulty behaviour. This work introduces a novel concept for wireless sensor network configuration considering fault tolerance, energy efficiency and convenience as primary goals while being tailored to user needs. It allows to ignore low-level details like node resources, network structures, node availability etc. and enables the programmer to work on a high abstraction level, namely the event itself including event related constraints. The definition of events characterising real world phenomena is of prominent use in sensor networks. The presented concept autonomously configures and monitors events, even if it requires to organise collaboration between nodes to deliver the results. The contribution of this work is threefold. An intuitive XML-based ESL simplifies event configuration to a level that is even suitable for non-professionals. It features hardware independent description elements to define complex phenomena and enhances these by tailor-made voting schemes and application constraints. Based on that, a novel, fully decentralised mechanism to autonomously set up distributed event detection called EDT and a cost efficient means to maintain such EDT, are presented. EDTs can be efficiently constructed on every device by using a tiny generating finite state machine requiring eight states only. It enables every node to self-divide event queries according to its own resources and self-adapt to the tasks assigned. Simultaneously, the EDT provides the interface for efficient collaboration using a lease-based publish/subscribe approach. The simulations clearly show that this concept works well and the applied collaboration scheme outperforms even idealised acknowledgement-based approaches. On top of the EDT, a means is developed that enhances the reliability of detection beyond the scope of Boolean event decision. It examines behavioural trends in sensor readings to indicate the significance of actual measurements in relation to the configured event. Measured data is investigated in detail to finally attach a significance indicator "is" to each event. This automatically generated indicator shall support users or overlaying systems in decision-making. In the example scenario based on data of real test cases, the "is" indicates a flaming fire 88 seconds and a smouldering fire 48 seconds before the threshold-based method triggers the alarm.}, subject = {Drahtloses Sensorsystem; Zuverl{\"a}ssigkeit; Zuverl{\"a}ssigkeit; Ereigniserkennung; Verbraucherfreundlichkeit; Drahtlose Sensornetze; Reliability; Event detection; Usability; Wireless Sensor Networks}, language = {en} } @phdthesis{Maaser2010, author = {Maaser, Michael}, title = {Design and realization of privacy guaranteeing means for context-sensitive systems}, isbn = {978-3-8322-9448-9}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-19596}, school = {BTU Cottbus - Senftenberg}, year = {2010}, abstract = {Privacy issues are becoming more and more important, especially since the cyber and the real world are converging up to certain extent when using mobile devices. Means that really protect privacy are still missing. The problem is, as soon as a user provides data to a service provider the user looses control over her/his data. The simple solution is not to provide any data but then many useful services, e.g., navigation applications, cannot be used. The dissertation addresses two aspects of privacy protection. The first aspect regards not producing private information if possible. Such unnecessary information are traces of access controlled service uses. Hence, one approach in this dissertation enables k-anonymous authorization for services uses. It equips the users of the system with trusted pseudonymous certificates reflecting their respective authorizations. Analogous to anonymous e-cash, the certificates are issued by a trusted authority with knowledge of the actual authorizations of an identified user. The certificates can be verified by any service supported by the trusted authority but without knowledge of the user's identity. Not even the issuing authority is able to reveal the users identity from the pseudonym of a certificate. Hence, service usage cannot be tracked, neither by the service nor by the authority. This protects the privacy of service usage behavior of users. The second aspect of privacy protection is to remain in control over private data released to others. Temporary release of private data is essential to context-sensitive services, which rely on these context data to provide or improve added value. Therefore, the dissertation designs a Privacy Guaranteeing Execution Container (PGEC), which enables applications to access private user data and guarantees that the user data is deleted as soon as the service or application is finished. Basically, the concept is that the application obtains access to the user data in a specially protected and certified environment, the PGEC. The PGEC also restricts the communication between the application and the service provider to what is explicitly allowed by the service user. In addition to those means, the PGEC also implements countermeasures against malicious attacks such as modified host systems and covert channel attacks, which might be misusing CPU load to signal data out of the PGEC. Thus, the PGEC guarantees a "one time use" of the provided private data.}, subject = {Digital Rights Management; Datenschutzfreundliche Techniken; Anonymit{\"a}t; DRM; Dateneinmalnutzung; Privacy enhancing techniques; Anonymity; DRM; One-time-use of data}, language = {en} } @phdthesis{Ehrig2014, author = {Ehrig, Marcus}, title = {Hardwareimplementierte latenzarme drahtlose Medienzugriffsprotokolle f{\"u}r h{\"o}chsten Datendurchsatz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-34828}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Der Fortschritt der Technik erm{\"o}glicht immer leistungsf{\"a}higere drahtlose Dienste mit hohen Anforderungen an Latenz, Jitter und {\"U}bertragungsgeschwindigkeit. Aktuelle digitale Protokolle f{\"u}r drahtgebundene hochaufl{\"o}sende Multimedia{\"u}bertragungen (HDMI, DisplayPort) oder Peripherieschnittstellen (USB, PCIe, SATA) in der Computertechnik erreichen Datenraten im Multi-Gigabit Bereich. Die {\"U}bertragung der Inhalte z.B. Filme, Musikstreaming oder Datei{\"u}bertragungen mit Hilfe breitbandiger drahtloser {\"U}bertragungsverfahren vereinfacht die kabellose „Installation" und die daraus folgende Benutzerfreundlichkeit (Mobilit{\"a}t) im Heimbereich (Indoor). Weiterhin werden Systeme mit hohen Datenraten und kleinen Latenzen unter 5 ms im Mobilfunkbereich ben{\"o}tigt, um Basisstationen (3G, LTE) mit dem Kernnetzwerk zu verbinden. Diese Backhaul-Verbindungen k{\"o}nnen auch im innerst{\"a}dtischen Bereich zum Aufbau von Small-Cell-Installationen genutzt werden, da nicht immer eine Kabelverlegung m{\"o}glich ist. Eine Verkettung der Verbindungen vergr{\"o}ßert den Abstand zum Zugangspunkt des Kernnetzes und stellt zus{\"a}tzliche Anschlußpunkte f{\"u}r Basisstationen bereit. Allerdings vergr{\"o}ßert sich auch die Latenz f{\"u}r die weiter entfernten Stationen. In dieser Arbeit wird ein MAC-Protokoll f{\"u}r hochratige und latenzarme drahtlose Verbindungen vorgestellt. Dazu werden sowohl Punkt-zu-Punkt- als auch Punkt-zu-Mehrpunkt-Verbindungen auf ihre speziellen Anforderungen bei der Implementierung der MAC-Komponenten in einer programmierbaren Hardware (FPGA) analysiert. Eine Integration des MAC-Protokolls zusammen mit einem OFDM-Basisbandprozessor mit Brutto-Datenraten gr{\"o}ßer 5 GBit/s erlaubt die {\"U}berpr{\"u}fung der Funktionalit{\"a}t sowie die Messung wichtiger Protokollparameter unter realen Einsatzbedingungen. Das vorgeschlagene Medienzugriffsprotokoll unterst{\"u}tzt den Einsatz von Beamsteering-Verfahren zur Suche von benachbarten Kommunikationsteilnehmern und den gleichzeitigen r{\"a}umlich getrennten Kanalzugriff mehrerer Kommunikationsteilnehmer. Eine Anwendungsschnittstelle f{\"u}r nutzerspezifische Implementierungen mit exklusivem Zugriff auf das {\"U}bertragungsmedium erleichtert die Integration zus{\"a}tzlicher Funktionalit{\"a}t wie z.B. eine hochaufl{\"o}sende Entfernungsmessung. Weiterhin wird ein Verfahren zur latenzarmen Detektierung und Umschaltung blockierter Pfade vorgestellt. Umfangreiche Simulationen best{\"a}tigen die Funktionalit{\"a}t des MAC-Protokolls in unterschiedlichen Szenarien mit und ohne {\"U}bertragungsfehler.}, subject = {Drahtlose Breitbandkommunikation; Drahtlose Medienzugriffssteuerung (MAC); Hochdirektive Antennen; Wireless Broadband Communication; Highly Directional Antennas; Breitbandkommunikation; Breitbandantenne; Funktechnik; Zugangsverfahren}, language = {de} }