@phdthesis{Lopacinski2017, author = {Lopacinski, Lukasz}, title = {Improving goodput and reliability of ultra-high-speed wireless communication at data link layer level}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-41272}, school = {BTU Cottbus - Senftenberg}, year = {2017}, abstract = {The design of 100 Gbps wireless networks is a challenging task. A serial Reed-Solomon decoder at the targeted data rate has to operate at ultra-fast clock frequency of 12.5 GHz to fulfill timing constraints of the transmission. Receiving a single Ethernet frame on the physical layer may be faster than accessing DDR3 memory. Moreover, data link layer of wireless systems has to cope with high bit error rate (BER). The BER in wireless communication can be several orders of magnitude higher than in wired systems. For example, the IEEE 802.3ba standard for 100 Gbps Ethernet limits the BER to 1e-12 at the data link layer. On the contrary, the BER of high-speed wireless RF-frontend working in the Terahertz band might be higher than 1e-3. Performing forward error correction on the state of the art FPGA (field programmable gate arrays) and ASICs requires a highly parallelized approach. Thus, new processing concepts have to be developed for fast wireless communication. Due to the mentioned factors, the data link layer for the wireless 100G communication has to be considered as new research, and cannot be adopted from other systems. This work provides a detailed case study about 100 Gbps data link layer design with the main focus on communication reliability improvements for ultra-high-speed wireless communication. Firstly, constraints of available hardware platforms are identified (memory capacity, memory access time, and logic area). Later, simulation of popular techniques used for data link layer optimizations are presented (frame fragmentation, frames aggregation, forward error correction, acknowledge frame compression, hybrid automatic repeat request, link adaptation, selective fragment retransmission). After that, data link layer FPGA accelerator processing ~116 Gbps of user data is presented. At the end, ASIC synthesis is considered and detailed statistics of consumed energy per bit are introduced. The research includes link adaptation techniques, which optimize goodput and consumed energy according to the channel BER. To the author's best knowledge, it is the first published data link layer implementation dedicated for 100 Gbps wireless communication shown anywhere in the world.}, subject = {Data link layer; Goodput; Field programmable gate array; Application specific integrated circuit; Forward error correction; Sicherungsschicht; Datendurchsatz; Feld programmierbare Gatter-Anordnung; Anwendungsspezifische integrierte Schaltung; Vorw{\"a}rtsfehlerkorrektur; Funknetz; Hardwareentwurf; Verbindungsschicht}, language = {en} } @phdthesis{Panić2014, author = {Panić, Goran}, title = {A methodology for designing low power sensor node hardware systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-33376}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {The design of embedded sensor node hardware systems is a challenging task driven by the increasing demands for low power, high efficiency, low cost and small size. These unique requirements make the usage of off-the-shelf general purpose microcontrollers fairly inefficient. For many wireless sensor network applications, the design of a dedicated low power sensor node microcontroller is the only way to answer specific application requirements. According to the trends in device, process and design technology, the development of sensor node devices is relying on a cheap planar bulk-CMOS technology, where power consumption is dominated by static power loss caused by high leakage currents. To keep the power at acceptable level, designers are compelled to apply the methodologies based on advanced low power techniques that target both static and dynamic power in the chip. The decisions made early in design phase are likely to determine the energy efficiency of the final design. Therefore, the choice of power saving strategy is the key challenge in designing energy-efficient sensor node hardware. This work presents a methodology that assists designers meeting the critical design decisions regarding power, early in the design process. The presented methodology extracts the activity profiles of single system components and applies them in the developed models for energy estimation of particular low power implementation. The energy estimation models account for the energy overhead introduced by specific low power techniques, enabling comprehensive exploration of system's energy efficiency in a given application scenario. Special attention is paid to the methodology utilization in typical wireless sensor network applications. Accordingly, the examples of activity profiling in wireless sensor node systems are presented. The proposed methodology is integrated within a power-driven design flow and applied to the design of an embedded sensor node microcontroller. This methodology is used to perform the cross comparison of alternative low power implementations for the target system architecture. The implementation relying on concurrent clock and power gating is selected as the most energy efficient and consequently realised. Power switching cells and power control logic have been designed and characterized. Also, the final system architecture, basic system components and applied design process are described. Finally, the developed power-gated sensor node microcontroller is implemented, fabricated and successfully tested. The chip measurements results are presented and analyzed. The analysis of different low power approaches applied to the target system architecture has shown large impact of clock gating on the system energy. In a given application scenario, the clock gating implementation has reduced 72 times the dynamic energy and 12 times the total energy of the system. The implementation of power gating technique has gained 2.8 times reduction of the leakage energy and 2 times reduction of the total system energy compared to the clock gating only implementation. The analysis of two alternative power gating approaches has emphasized the significance of partitioning in power-gated design. A heuristic partitioning that combines two specific blocks having successive activity phases into a single power domain, thereby reducing design complexity and chip area, has been shown to have positive impact on the energy efficiency of the target design.}, subject = {Wireless sensor networks; Sensor node; Low power design; Power gating; ASIC; Drahtlose Sensornetze; Sensorknoten; Energieeffizientes Design; Stromspartechniken; Chipdesign; Drahtloses Sensorsystem; Mikroprozessor; Eingebettetes System}, language = {en} } @phdthesis{Wang2008, author = {Wang, Li}, title = {Millimeter-wave Integrated Circuits in SiGe:C Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-5993}, school = {BTU Cottbus - Senftenberg}, year = {2008}, abstract = {During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.}, subject = {Integrierte Mikrowellenschaltung; Silicium; Germanium; MMiC; Integrierte Millimeterwellenschaltung; Millimeter-wave; IC; SiGe; HBT; W-band}, language = {en} } @phdthesis{Skoncej2014, author = {Skoncej, Patryk}, title = {Investigation of methods for increasing the reliability of highly integrated non-volatile memories on system level}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-35122}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Conventional semiconductor memories are facing many challenges concerning their yield, reliability, testability, and manufacturability as the feature size decreases. Although they are used in the vast majority of electronic devices, their applicability for upcoming digital systems is questionable. On the other hand, due to unprecedented development of mobile devices even faster, denser, and more power-efficient semiconductor memories are required. As a consequence, many researchers and system designers are seeking new memory solutions. The greatest attention is paid to solid-state, non-volatile memories (NVMs) such as PCRAMs, MRAMs/STT-MRAMs, FeRAMs, and RRAMs. Due to their promising features like non-volatility, low-power consumption, and great scalability they are expected to meet the challenging demands of future digital systems. Unfortunately, despite all advantages they offer, emerging NVMs pose some peculiar characteristics like limited endurance, variable data retention time, or vulnerability to external factors. On top of that, they are still in early-maturity state where their fabrication processes are not of high quality and are prone to high variations. Because of that, emerging NVMs may suffer from permanent faults which can occur right after production or in the field, during their operational time. As a consequence, the reliability of new memory technologies requires special management and great improvement. The thesis introduces system-level approach aimed at comprehensive reliability management of existing and emerging NVMs. It presents novel on-line repair techniques which focus on specific issues of NVMs. The block-level repair manages post-production faults in the memory array. The word-level repair aims at hard faults caused by wear-out memory cells. Finally, the error-correcting code with increased hard-error correction capability handles soft and hard errors in the memory array. Because proposed techniques are based on similar principles, they can be combined into a consistent system. Depending on the way how they are connected, different repair schemes can be achieved. Moreover, by merging them into the system a synergistic effect can be produced where the achieved memory reliability improvement is greater than the sum of reliability improvements achieved with their standalone implementations. Further in the thesis, such a consistent repair system is presented. Next, its effectiveness, repair capabilities, and applicability for an embedded system are evaluated. In addition, the achieved synergistic effect is described and quantified}, subject = {Built-in self-repair; Error-correcting code; Non-volatile memory; Eingebaute Selbstreparatur; Fehlerkorrekturcode; Nichtfl{\"u}chtiger Speicher; Nichtfl{\"u}chtiger Speicher; Fehlerkorrekturcode}, language = {en} } @phdthesis{Borokhovych2011, author = {Borokhovych, Yevgen}, title = {High-speed data capturing components for Super Resolution Maximum Length Binary Sequence UWB Radar}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-24501}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {Within framework of UKoLoS project the new Super Resolution Maximum Length Binary Sequence UWB Radar (M-sequence radar) was developed. The radar consists of an M-sequence generator, transmitter front-end, receiver front-end, data capturing device and data processing blocks, whose design responsibilities were carried out by four institutions. In this thesis the design and measurements of the data capturing device components is described. Logically the data capturing device can be divided into three parts; a capturing part, realized with the high-speed analog-to-digital converter, a predictor, realized with the high-speed digital-to-analog converter and a subtraction amplifier, which in this particular work is integrated into the receiver front-end. The main challenge of the work is to implement the A/D converter, which works at full speed of the radar. Despite the radar architecture allows capturing data with undersampling, it leads to waste of transmitted energy. Therefore the ADC has to capture reflected signal with the full system clock rate of 10 GHz and should have a full Nyquist 5 GHz effective resolution bandwidth. Implementation of the conventional 4-bit full flash ADC with specified bandwidth is not possible in the IHP SiGe BiCMOS technology because some critical blocks, namely the reference network, can not achieve 5 GHz effective resolution bandwidth. To overcome this problem a new configuration of the differential reference network is proposed. The new reference network has a segmented, free configurable architecture. As extreme case it can be realized as a full parallel network and in such configuration the maximal bandwidth can be achieved. The proposed network was implemented in the A/D converter and measured. The bandwidth of the ADC with new network is several times higher than the bandwidth of the conventional ADC,while keeping power dissipation the same. Further the proposed network has possibility to equalize the bandwidth in each output node and in that way optimize overall power dissipation. The other advantage is the possibility of electronic calibration of separate voltage shift in the network. The second component of the data capturing device is the D/A converter, which is required to have the accuracy which corresponds to full accuracy of the data capturing device, better than 0.2\% in our case. Measurements showed that error due to mismatch of the components was 10 times higher than required. To meet the accuracy specification an external off-line calibration of the DAC was implemented. Using calibration the predictor errors less than 0.15\% were achieved.}, subject = {Analog-Digital-Umsetzer; Digital-Analog-Umsetzer; Analog-Digital-Wandler; Digital-Analog-Wandler; Folge-HalteVerst{\"a}rker; M-Sequenz UWB-Radar; Analog-to-digital converter; Full flash; Track-and-hold amplifier; Reference network}, language = {en} } @phdthesis{Knobloch2018, author = {Knobloch, Florian}, title = {Energieeffiziente Beleuchtung unter Ber{\"u}cksichtigung einer verteilten Steuerung und eines redundanten Kommunikationssystems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-45480}, school = {BTU Cottbus - Senftenberg}, year = {2018}, abstract = {Das Thema siedelt sich im Bereich Smart-City an. Die Einsparung von Energie ist in der {\"o}ffentlichen Straßenbeleuchtung von Interesse. Die Intention ist eine Automatisierung der Beleuchtungsanlage unter Nutzung einer drahtlosen Kommunikation. Ziel ist die Untersuchung des Einsparpotentials, der ben{\"o}tigten Datenraten und der Robustheit. Die physiologischen Bed{\"u}rfnisse des Verkehrsteilnehmers zur Einhaltung der Verkehrssicherheit werden konsequent ber{\"u}cksichtigt. Die Umr{\"u}stung auf eine automatisierte Beleuchtung lohnt sich besonders in l{\"a}ndlichen Regionen oder Anliegerstraßen, wobei in Tempo-30-Zonen eine optimale Energieeffizienz existiert. Aufgrund eines beleuchteten Anhalteweges existieren maximale Einsparungen. Das Optimum wird durch eine Extremwertanalyse bewiesen und ausf{\"u}hrlich untersucht. Die Einsparung h{\"a}ngt haupts{\"a}chlich von der Verkehrsst{\"a}rke, der Verkehrsgeschwindigkeit und der Dimmstufe ab. Die lineare Abh{\"a}ngigkeit von der Dimmstufe wird bei einer geringen Verkehrsst{\"a}rke durch eine Grenzwertanalyse gezeigt. 70 \% Energie l{\"a}sst sich im Gegensatz zu einer Dauerbeleuchtung mit typischen Parametern sparen. Im Gegensatz zu anderen L{\"o}sungskonzepten erreicht das entwickelte Moving-Light-System Mehreinsparungen von bis zu 23 \%. Lichtplaner und Kommunen k{\"o}nnen {\"o}rtliche Sparpotentiale mit dem neuen Modell berechnen, um zu pr{\"u}fen ob sich eine Umr{\"u}stung {\"u}berhaupt lohnen w{\"u}rde. Die ben{\"o}tigte Steuerung wird abstrakt beschrieben und mit Simulink verifiziert. Zur Verbesserung der Robustheit werden das schon vorhandene Licht und die ggf. schon vorhandenen Detektoren als redundantes {\"U}bertragungsmedium untersucht. Die Nutzung des sichtbaren Lichtes lohnt sich, wenn gleichzeitig solare Energiegewinne gew{\"u}nscht sind, weil der notwendige Aperturdurchmesser des Detektors im Bereich mehrerer 10 cm liegt. Neben der optischen Kommunikation wird die Helligkeit benachbarter Leuchten automatisch mitgemessen. Dies erm{\"o}glicht die Detektion von Fehlerzust{\"a}nden f{\"u}r eine verbesserte Wartung oder f{\"u}r die Aktivierung m{\"o}glicher redundanter Fail-Safe-Funktionen. Eine hop-weise Lokalisierung wird in dem Multihopsystem ausgenutzt, damit die Steuerung ohne Kartenmaterial und Kompasssensor auskommt. Weitere Arbeit besteht bei der Quantifizierung der Eingangsparameter vom Menschen um den Lichtbedarf zu decken. Aufgrund der anwendungsorientierten Problemstellung liegt ein Querschnittsthema aus der Verkehrswissenschaft, Automatisierungstechnik, Kommunikationstechnik und Optik vor. Es wird eine Forschungshypothese vorangestellt. Sie dient als Leitfaden und stellt die wesentlichen Erkenntnisse vorweg.}, subject = {Energieeffiziente Beleuchtung; Nutzerzentriertes Design; Echtzeit; Kabellose Kommunikation; Intelligente Straßenbeleuchtung; Energy efficient systems; User-centred design; Location-aware applications; Real-time wireless communication; Intelligent street lighting; Straßenbeleuchtung; Energieeffizienz; Smart City; Kommunikationssystem}, language = {de} }