@phdthesis{Borokhovych2011, author = {Borokhovych, Yevgen}, title = {High-speed data capturing components for Super Resolution Maximum Length Binary Sequence UWB Radar}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-24501}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {Within framework of UKoLoS project the new Super Resolution Maximum Length Binary Sequence UWB Radar (M-sequence radar) was developed. The radar consists of an M-sequence generator, transmitter front-end, receiver front-end, data capturing device and data processing blocks, whose design responsibilities were carried out by four institutions. In this thesis the design and measurements of the data capturing device components is described. Logically the data capturing device can be divided into three parts; a capturing part, realized with the high-speed analog-to-digital converter, a predictor, realized with the high-speed digital-to-analog converter and a subtraction amplifier, which in this particular work is integrated into the receiver front-end. The main challenge of the work is to implement the A/D converter, which works at full speed of the radar. Despite the radar architecture allows capturing data with undersampling, it leads to waste of transmitted energy. Therefore the ADC has to capture reflected signal with the full system clock rate of 10 GHz and should have a full Nyquist 5 GHz effective resolution bandwidth. Implementation of the conventional 4-bit full flash ADC with specified bandwidth is not possible in the IHP SiGe BiCMOS technology because some critical blocks, namely the reference network, can not achieve 5 GHz effective resolution bandwidth. To overcome this problem a new configuration of the differential reference network is proposed. The new reference network has a segmented, free configurable architecture. As extreme case it can be realized as a full parallel network and in such configuration the maximal bandwidth can be achieved. The proposed network was implemented in the A/D converter and measured. The bandwidth of the ADC with new network is several times higher than the bandwidth of the conventional ADC,while keeping power dissipation the same. Further the proposed network has possibility to equalize the bandwidth in each output node and in that way optimize overall power dissipation. The other advantage is the possibility of electronic calibration of separate voltage shift in the network. The second component of the data capturing device is the D/A converter, which is required to have the accuracy which corresponds to full accuracy of the data capturing device, better than 0.2\% in our case. Measurements showed that error due to mismatch of the components was 10 times higher than required. To meet the accuracy specification an external off-line calibration of the DAC was implemented. Using calibration the predictor errors less than 0.15\% were achieved.}, subject = {Analog-Digital-Umsetzer; Digital-Analog-Umsetzer; Analog-Digital-Wandler; Digital-Analog-Wandler; Folge-HalteVerst{\"a}rker; M-Sequenz UWB-Radar; Analog-to-digital converter; Full flash; Track-and-hold amplifier; Reference network}, language = {en} } @phdthesis{Sun2009, author = {Sun, Yaoming}, title = {Design of an integrated 60 GHz Transceiver Front-End in SiGe:C BiCMOS Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-11384}, school = {BTU Cottbus - Senftenberg}, year = {2009}, abstract = {This thesis describes the complete design of a low cost 60 GHz front end in SiGe BiCMOS technology. It covers the topics of a system plan, designs of building blocks, designs of application boards and real environment tests. Different LNA and mixer topologies have been investigated and fabricated. Good agreements between measurements and simulations have been achieved by using the self-developed component models. A transceiver front end system is built based on these blocks. A heterodyne architecture with a 5 GHz IF is adopted because it is compatible with the standard IEEE 802.11a, which allows the reuse of some existing building blocks of the 5 GHz transceiver. The transceiver chips are assembled onto application boards and connected by bond-wires. Bond-wire inductances have been minimized by using a cavity and compensated by an on board structure. The front end has been tested by both QPSK and OFDM signals in an indoor environment. Clear constellations have been measured. This was the first silicon based 60 GHz demonstrator in Europe and the second in the world.}, subject = {MMIC; Hochfrequenzschaltung; Transceiver; 60-GHz-Transceiver; MMIC; Integrierte Hochfrequenzschaltungen; Einchip-L{\"o}sung; Drahtlose Kommunikation; 60 GHz transceiver; MMIC; RFIC; Single chip solution; Wireless communication}, language = {en} } @phdthesis{Veleski2022, author = {Veleski, Mitko}, title = {A cross-layer framework for adaptive processor-based systems regarding error resilience and power efficiency}, doi = {10.26127/BTUOpen-6145}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-61450}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1\% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15\%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.}, subject = {Processor; Cross-layer; Power; Resilience; Prozessoren; Energieeffizienz; Leistungseffizienz; Fehlerresilienz; Prozessor; Modell; Energieeffizienz; Fehlertoleranz}, language = {en} } @phdthesis{Buechner2020, author = {B{\"u}chner, Steffen}, title = {Applying the stream-processing paradigm to ultra high-speed communication systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-52462}, school = {BTU Cottbus - Senftenberg}, year = {2020}, abstract = {In the last 30 years, communication became one of the most important pillars of our civilization. Every day terabytes of information are moved wired and wireless between computers. In order to transport this amount of data, researchers and industry increase the data rates of the underlying communication networks with impressive speed. However, such ultra-high data rates are unavailable at the communication endpoints. One reason why ultra-high data rates are still not available for the communication endpoints is their inability to handle the protocol processing at this data rate. In order to enable communication endpoints to process high-volume data streams, the protocol processing has to be parallelized and optimized on all processing levels. However, parallelization and optimization are cumbersome tasks, which are further complicated as the protocol processing is traditionally carried out by the operating system. This thesis aims at circumventing these problems by moving the protocol processing into external processing hardware and interpreting communication protocols as stream processing problems. In order to achieve ultra-high data rates at the communication endpoints, a protocol stream processing design approach was developed and evaluated. The design process is separated into implementation, soft real-time analysis, parallelization, and mapping steps, which allow a scalable protocol implementation without paradigm changes. Furthermore, a data link protocol for 100 Gbit/s wireless was developed and implemented with the new stream processing design concept, in order to show its feasibility. The data link protocol is configurable for different communication conditions and easy to parallelize by providing different granularities of packets. The proposed design-process has shown to be suitable for uncovering bottlenecks and helping with debugging the individual stages of the protocol.}, subject = {Stream processing; Ultra high speed communication systems; Communication protocols; Wireless communication; End2End100; Stromverarbeitung; Ultra-Hoch-Geschwindigkeits-Kommunikationssysteme; Kommunikationsprotokolle; Drahtlose Kommunikation; Kommunikationsprotokoll; Protokollverarbeitung ; Hochgeschwindigkeitskommunikation; End2End100}, language = {en} } @phdthesis{Knobloch2018, author = {Knobloch, Florian}, title = {Energieeffiziente Beleuchtung unter Ber{\"u}cksichtigung einer verteilten Steuerung und eines redundanten Kommunikationssystems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-45480}, school = {BTU Cottbus - Senftenberg}, year = {2018}, abstract = {Das Thema siedelt sich im Bereich Smart-City an. Die Einsparung von Energie ist in der {\"o}ffentlichen Straßenbeleuchtung von Interesse. Die Intention ist eine Automatisierung der Beleuchtungsanlage unter Nutzung einer drahtlosen Kommunikation. Ziel ist die Untersuchung des Einsparpotentials, der ben{\"o}tigten Datenraten und der Robustheit. Die physiologischen Bed{\"u}rfnisse des Verkehrsteilnehmers zur Einhaltung der Verkehrssicherheit werden konsequent ber{\"u}cksichtigt. Die Umr{\"u}stung auf eine automatisierte Beleuchtung lohnt sich besonders in l{\"a}ndlichen Regionen oder Anliegerstraßen, wobei in Tempo-30-Zonen eine optimale Energieeffizienz existiert. Aufgrund eines beleuchteten Anhalteweges existieren maximale Einsparungen. Das Optimum wird durch eine Extremwertanalyse bewiesen und ausf{\"u}hrlich untersucht. Die Einsparung h{\"a}ngt haupts{\"a}chlich von der Verkehrsst{\"a}rke, der Verkehrsgeschwindigkeit und der Dimmstufe ab. Die lineare Abh{\"a}ngigkeit von der Dimmstufe wird bei einer geringen Verkehrsst{\"a}rke durch eine Grenzwertanalyse gezeigt. 70 \% Energie l{\"a}sst sich im Gegensatz zu einer Dauerbeleuchtung mit typischen Parametern sparen. Im Gegensatz zu anderen L{\"o}sungskonzepten erreicht das entwickelte Moving-Light-System Mehreinsparungen von bis zu 23 \%. Lichtplaner und Kommunen k{\"o}nnen {\"o}rtliche Sparpotentiale mit dem neuen Modell berechnen, um zu pr{\"u}fen ob sich eine Umr{\"u}stung {\"u}berhaupt lohnen w{\"u}rde. Die ben{\"o}tigte Steuerung wird abstrakt beschrieben und mit Simulink verifiziert. Zur Verbesserung der Robustheit werden das schon vorhandene Licht und die ggf. schon vorhandenen Detektoren als redundantes {\"U}bertragungsmedium untersucht. Die Nutzung des sichtbaren Lichtes lohnt sich, wenn gleichzeitig solare Energiegewinne gew{\"u}nscht sind, weil der notwendige Aperturdurchmesser des Detektors im Bereich mehrerer 10 cm liegt. Neben der optischen Kommunikation wird die Helligkeit benachbarter Leuchten automatisch mitgemessen. Dies erm{\"o}glicht die Detektion von Fehlerzust{\"a}nden f{\"u}r eine verbesserte Wartung oder f{\"u}r die Aktivierung m{\"o}glicher redundanter Fail-Safe-Funktionen. Eine hop-weise Lokalisierung wird in dem Multihopsystem ausgenutzt, damit die Steuerung ohne Kartenmaterial und Kompasssensor auskommt. Weitere Arbeit besteht bei der Quantifizierung der Eingangsparameter vom Menschen um den Lichtbedarf zu decken. Aufgrund der anwendungsorientierten Problemstellung liegt ein Querschnittsthema aus der Verkehrswissenschaft, Automatisierungstechnik, Kommunikationstechnik und Optik vor. Es wird eine Forschungshypothese vorangestellt. Sie dient als Leitfaden und stellt die wesentlichen Erkenntnisse vorweg.}, subject = {Energieeffiziente Beleuchtung; Nutzerzentriertes Design; Echtzeit; Kabellose Kommunikation; Intelligente Straßenbeleuchtung; Energy efficient systems; User-centred design; Location-aware applications; Real-time wireless communication; Intelligent street lighting; Straßenbeleuchtung; Energieeffizienz; Smart City; Kommunikationssystem}, language = {de} } @phdthesis{Babić2021, author = {Babić, Milan}, title = {GALS methodology for substrate noise reduction in mixed-signal integrated circuits}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-57264}, school = {BTU Cottbus - Senftenberg}, year = {2021}, abstract = {Mixed signal integrated circuits (MSICs) contain both analog and digital circuitry, integrated together on the same die. While this integration brings many benefits, it also gives rise to the issue of substrate noise coupling between the noisy digital circuitry and noise-sensitive analog circuitry. In order to counteract this issue, various substrate noise reduction methodologies had been developed so far. This thesis explores a new approach in substrate noise reduction - using a GALS (globally-synchronous, locally-asynchronous) design strategy for the digital part of a MSIC, in order to reduce the noise generation at its source. GALS architectures consist of several locally synchronous modules (LSMs) which communicate asynchronously to each other. By converting an initially synchronous architecture of digital circuitry into a GALS architecture, simultaneous switching noise generated by this circuitry can be reduced. While GALS had already been used for reducing other types of simultaneous switching noise, this is, to the best of the author's knowledge, the first attempt to develop a GALS-based methodology for substrate noise reduction. In order to be able to theoretically analyze GALS-based methodologies for substrate noise suppression, corresponding models at high abstraction level for substrate noise generation and substrate noise propagation in lightly doped substrates (which is a type of substrate mostly used for MSICs) have been developed. These models have further been used for developing two new GALS-based substrate noise reduction methodologies: harmonic-balanced plesiochronous GALS partitioning (HB) and harmonic-and-area-based plesiochronous GALS partitioning with power domain separation (HAB). A theoretical analysis has shown that HB can reach substrate noise attenuation of up to 20log⁡(M), where M is the number of LSMs of the resulting GALS system. On the other hand, the attenuation achievable by HAB depends on the distribution of switching current harmonics and area among the partitions, as well as from the substrate itself. For each of the two methodologies, a suitable partitioning procedure for a practical application has been developed; these partitionig procedures have been numerically evaluated in MATLAB. HB has further been embedded within the EMIAS CAD tool, where it has been evaluated on a real design example - a wireless sensor node. A special case of HAB for low frequencies has been applied for developing a test chip called SGE (power domain Separation and Galsification Experiment). The measurements on silicon have proved the applicability of the methodology.}, subject = {GALS; Plesiochronous clocking; Simultaneous switching noise; Substrate noise; MSIC; Plesiochrones Takten; Simultanes Schaltrauschen; Substratrauschen; Partitionierung; LSM; GALS; Mixed-Signal-Schaltung; Rauschunterdr{\"u}ckung}, language = {en} } @phdthesis{Dietrich2021, author = {Dietrich, Steven}, title = {Methods of evaluation and improvement on cascaded wired and wireless real-time communication networks for factory automation}, doi = {10.26127/BTUOpen-5483}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-54833}, school = {BTU Cottbus - Senftenberg}, year = {2021}, abstract = {Factory automation applications require a communication system that concurrently supports them with determinism, reliability, short communication cycles, and precise synchronization as well as mobility and extensibility. However, neither currently employed wired nor available wireless communication networks support all of these requirements at once. On the one hand, wired networks lack mobility and extensibility. On the other hand, wireless networks do not support reliability or determinism due to the stochastic nature of wireless channels. Moreover, none of the available wireless networks enable transmission latencies of 1 ms and below. Therefore, they cannot support the required short communication cycles. However, various research initiatives and the currently developed 5G standard promise to overcome these limitations at least partially. Nevertheless, even a corresponding wireless network will not directly replace all wired connections, but will initially be used for subsections of the data transmission, where e.g. mobility is of utmost importance. Accordingly, cascaded communication networks consisting of hierarchically ordered, wired and wireless subnetworks will emerge. In this thesis, we investigate effects and dependencies of such a cascading for the real-time communication of factory automation applications. Therefore, we have to find methods to interconnect arbitrary wired and wireless communication networks such that we can maintain the reliable real-time performance of wired subnetworks and the mobility of wireless subnetworks without, or at most with minimal performance degradation. Ideally, with a cascaded network, no hardware or software adjustments will be necessary compared to the individual networks deployed today. Based on a delimiting review of different application areas and a dedicated use case analysis of typical factory automation applications, we derive the most challenging requirements that have to be fulfilled by cascaded communication networks. According to this review, we present several methods to reduce the overall transmission latency in cascaded networks. Starting with analyzing different interface concepts and continuing with frame conversion methods, we achieve a decision-making basis to select dedicated subnetworks for a cascaded network that can be used for closed-loop control applications. Additionally, we develop methods to optimize the parametrization of individual subnetworks with respect to the overall communication, such that the end-to-end transmission latency can be drastically reduced. For verification, we design a generic model for analyzing the timing behavior of arbitrary communication networks and verify it based on an analysis of a machine tool application scenario. Additional measurements based on a real demonstrator implementation corroborate that, in industrial application, cascaded communication networks can provide competitive performance compared to the currently used wired networks.}, subject = {Cascaded networks; Factory automation; Real-time communication; Kaskadiertes Netzwerk; Fabrikautomatisierung; Echtzeitkommunikation; Telekommunikationsnetz; Echtzeitverarbeitung; Automatisierung}, language = {en} } @phdthesis{Hasani2021, author = {Hasani, Alireza}, title = {High-throughput QC-LDPC codes for next-generation wireless communication systems}, doi = {10.26127/BTUOpen-5819}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-58194}, school = {BTU Cottbus - Senftenberg}, year = {2021}, abstract = {Wireless communication has become an indispensable part of our life and the demand for achieving higher throughput with lower energy consumption is ever growing. The ambitious throughput of 100 Gb/s and beyond is now becoming a modest goal thanks to comprehensive advances in transmission technologies and protocols. One important aspect of these advances is with regard to channel coding methods and the ability to detect and correct errors at the receiver. Computations needed by such methods become generally more complicated as they become more powerful in their performance. This imposes a great challenge for researchers attempting to devise practical methods for encoding and decoding Forward-error Correction (FEC) techniques tailored for high-throughput scenarios. In this work we focus on high-throughput Quasi-Cyclic LDPC (QC-LDPC) codes, as they have been selected as one of the main FEC techniques for the two major next generation wireless technologies, namely Wi-Fi 6 (IEEE 802.11ax) and 5G. Our target is to develop complete encoding and decoding design for these codes in order to reach the throughput of 100 Gb/s with affordable power consumption. Toward this goal, we investigate first the appropriate encoder design for these codes which can be used at such high data-rate with reasonably low power consumption. Then we propose several novel ideas for improving the decoding performance and complexity of QC-LDPC codes. The proposed novel ideas collectively facilitate a decoder able to run at 50 Gb/s with less than 12 pJ/b energy consumption for a Latin squares QC-LDPC code. All the proposed methods are practical and implementable and their effectiveness are showcased by either Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) synthesis.}, subject = {LDPC decoding; High-throughput decoding; Belief propagation; LDPC-Decodierung; Decodierung mit hohem Durchsatz; Glaubensverbreitung; Datenfunknetz; Kanalcodierung; Low-Density-Parity-Check-Code; Vorw{\"a}rtsfehlerkorrektur}, language = {en} } @phdthesis{Piz2011, author = {Piz, Maxim}, title = {Wideband OFDM System for Indoor Communication at 60 GHz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-22909}, school = {BTU Cottbus - Senftenberg}, year = {2011}, abstract = {The license-free 60 GHz band enables a new breed of wireless networks offering data rates in the range of one to a few Gigabit per second over short distances. This thesis investigates the performance of a 60 GHz system using coded OFDM modulation and directive antennas for the transmitter and receiver. The study includes the impact of the 60 GHz propagation channel, impairments of a frontend in Si-Ge technology and considerations with respect to an efficient implementation. A major part of the work consists in the specification of a physical layer, which is optimized for the given wireless link and enables an implementation with programmable logic devices at moderate clock speed. For the selection of a channel code, the performance of two coding schemes is compared for the 60 GHz channel. The first scheme consists of a standard convolutional code and an outer Reed-Solomon code, whereas the second scheme is made up of an LDPC code with similar complexity. The interleaving scheme for the convolutional code is optimized to yield best performance. Furthermore, algorithms are developed and simulated for all essential system components of the OFDM receiver. The implementation of these components is also considered. A new synchronization scheme is introduced, which offers a high degree of robustness at low complexity. In this scheme, the fine timing synchronization shares the same hardware resources as the channel estimator. This approach results in a significant reduction of chip area. A new tracking algorithm is developed, which adequately compensates for the fluctuations of carrier phase, timing and channel impulse response. Finally, the implementation of the FFT and Viterbi decoder is discussed. The system architecture of the receiver requires a high degree of parallel processing and uses a deep processing pipeline to keep the clock frequency low. It is shown how to combine the system components into an efficient system under these conditions. The performance of the complete system is investigated for the static and time-variant channel. It is shown that despite the low complexity and high latency, the system achieves good performance. The baseband processor has been realized as a narrowband version with 400 MHz channels and broadband version with 2 GHz channels and improved algorithms. This has been done on an FPGA platform.}, subject = {Drahtloses lokales Netz; OFDM; OFDM; 60 GHz Kommunikation; WPAN; WLAN; Basisband Design; OFDM; 60 GHz Communication; WPAN; WLAN; Baseband Design}, language = {en} } @phdthesis{Ehrig2014, author = {Ehrig, Marcus}, title = {Hardwareimplementierte latenzarme drahtlose Medienzugriffsprotokolle f{\"u}r h{\"o}chsten Datendurchsatz}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-34828}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Der Fortschritt der Technik erm{\"o}glicht immer leistungsf{\"a}higere drahtlose Dienste mit hohen Anforderungen an Latenz, Jitter und {\"U}bertragungsgeschwindigkeit. Aktuelle digitale Protokolle f{\"u}r drahtgebundene hochaufl{\"o}sende Multimedia{\"u}bertragungen (HDMI, DisplayPort) oder Peripherieschnittstellen (USB, PCIe, SATA) in der Computertechnik erreichen Datenraten im Multi-Gigabit Bereich. Die {\"U}bertragung der Inhalte z.B. Filme, Musikstreaming oder Datei{\"u}bertragungen mit Hilfe breitbandiger drahtloser {\"U}bertragungsverfahren vereinfacht die kabellose „Installation" und die daraus folgende Benutzerfreundlichkeit (Mobilit{\"a}t) im Heimbereich (Indoor). Weiterhin werden Systeme mit hohen Datenraten und kleinen Latenzen unter 5 ms im Mobilfunkbereich ben{\"o}tigt, um Basisstationen (3G, LTE) mit dem Kernnetzwerk zu verbinden. Diese Backhaul-Verbindungen k{\"o}nnen auch im innerst{\"a}dtischen Bereich zum Aufbau von Small-Cell-Installationen genutzt werden, da nicht immer eine Kabelverlegung m{\"o}glich ist. Eine Verkettung der Verbindungen vergr{\"o}ßert den Abstand zum Zugangspunkt des Kernnetzes und stellt zus{\"a}tzliche Anschlußpunkte f{\"u}r Basisstationen bereit. Allerdings vergr{\"o}ßert sich auch die Latenz f{\"u}r die weiter entfernten Stationen. In dieser Arbeit wird ein MAC-Protokoll f{\"u}r hochratige und latenzarme drahtlose Verbindungen vorgestellt. Dazu werden sowohl Punkt-zu-Punkt- als auch Punkt-zu-Mehrpunkt-Verbindungen auf ihre speziellen Anforderungen bei der Implementierung der MAC-Komponenten in einer programmierbaren Hardware (FPGA) analysiert. Eine Integration des MAC-Protokolls zusammen mit einem OFDM-Basisbandprozessor mit Brutto-Datenraten gr{\"o}ßer 5 GBit/s erlaubt die {\"U}berpr{\"u}fung der Funktionalit{\"a}t sowie die Messung wichtiger Protokollparameter unter realen Einsatzbedingungen. Das vorgeschlagene Medienzugriffsprotokoll unterst{\"u}tzt den Einsatz von Beamsteering-Verfahren zur Suche von benachbarten Kommunikationsteilnehmern und den gleichzeitigen r{\"a}umlich getrennten Kanalzugriff mehrerer Kommunikationsteilnehmer. Eine Anwendungsschnittstelle f{\"u}r nutzerspezifische Implementierungen mit exklusivem Zugriff auf das {\"U}bertragungsmedium erleichtert die Integration zus{\"a}tzlicher Funktionalit{\"a}t wie z.B. eine hochaufl{\"o}sende Entfernungsmessung. Weiterhin wird ein Verfahren zur latenzarmen Detektierung und Umschaltung blockierter Pfade vorgestellt. Umfangreiche Simulationen best{\"a}tigen die Funktionalit{\"a}t des MAC-Protokolls in unterschiedlichen Szenarien mit und ohne {\"U}bertragungsfehler.}, subject = {Drahtlose Breitbandkommunikation; Drahtlose Medienzugriffssteuerung (MAC); Hochdirektive Antennen; Wireless Broadband Communication; Highly Directional Antennas; Breitbandkommunikation; Breitbandantenne; Funktechnik; Zugangsverfahren}, language = {de} }