@phdthesis{Petrovic2013, author = {Petrovic, Vladimir}, title = {Design methodology for highly reliable digital ASIC designs applied to network-centric system middleware switch processor}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29620}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.}, subject = {Kundenspezifische Schaltung; Schaltungsentwurf; Fehlertoleranz; Entwurfsmethodik; Single Event Effects; Latchup Schutz; ASIC Entwurf; Fault-tolerance; Design methodology; Single event effects; Latchup protection; ASIC design}, language = {en} } @phdthesis{Veleski2022, author = {Veleski, Mitko}, title = {A cross-layer framework for adaptive processor-based systems regarding error resilience and power efficiency}, doi = {10.26127/BTUOpen-6145}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-61450}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1\% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15\%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.}, subject = {Processor; Cross-layer; Power; Resilience; Prozessoren; Energieeffizienz; Leistungseffizienz; Fehlerresilienz; Prozessor; Modell; Energieeffizienz; Fehlertoleranz}, language = {en} } @phdthesis{Simevski2014, author = {Simevski, Aleksandar}, title = {Architectural framework for dynamically adaptable multiprocessors regarding aging, fault tolerance, performance and power consumption}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-32572}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {Despite the numerous benefits that Integrated Circuit (IC) technology downscaling brings, it also introduces many challenges. First of all, IC dependability is lowering: both lifetime reliability and resilience to single event effects is decreasing. Another major problem is the increased power consumption. On the other hand, the vast available space enables integrating hundreds of processor cores in a single chip! Multiprocessing is for over a decade the main architectural trend because of two reasons. Firstly, the performance of single processors gained by architectural innovations reached the upper limit i.e., the point of diminishing returns. Secondly, the operating frequency could not be increased due to the excessive power consumption, as pointed out. This work proposes a multiprocessor architectural framework that addresses many challenges related to dependability, power consumption and performance. The key idea is dynamical adaptation to the application requirements of fault tolerance and performance, which is possibly done at the lowest rates of aging and power dissipation. The application may select one of the three basic operating modes: de-stress, fault-tolerant and high-performance. De-stress mode prolongs multiprocessor lifetime and reduces power consumption by using core gating patterns that systematically power- or clock-off entire cores in the multiprocessor. These patterns use the information supplied by novel IC aging monitors. Fault-tolerant mode, on the other hand, increases error resilience by forming core-level NMR (N-modular redundant) systems using the multiprocessor cores. That is, entire cores are tightly synchronized to execute the same task simultaneously. Voting is done on each clock cycle using special, programmable NMR voters. Core-level NMR enables masking faults without invoking recovery procedures which is appreciated by timing-critical, or, real-time applications. Finally, high-performance mode is used for boosting multiprocessor performance. The framework is evaluated using a novel environment for automated fault injection, as well as a novel multiprocessor verification platform. A vast number of experiments were made which led to closed-form expressions that determine the number of cores N required to survive the projected mission time, given the fault rate. Moreover, a newly-developed method for lifetime evaluation based on the Weibul distribution shows the benefits of using core gating patterns. E.g., the new Youngest-First Round-Robin (YFRR) pattern enables up to 31\% increase in system's lifetime compared to a simple Round-Robin.}, subject = {Dependable multiprocessor; Multiprocessor lifetime; Multiprocessor fault tolerance; Zuverl{\"a}ssige Multiprozessoren; Multiprozessoren Alterung; Mehrprozessorsystem; Fehlertoleranz; Fehlererkennung}, language = {en} } @phdthesis{Augustin2012, author = {Augustin, Michael}, title = {Spezifische Fehlertoleranz f{\"u}r kombinatorische und sequentielle Schaltungen}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-26931}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {In dieser Arbeit wird ein neues Konzept f{\"u}r den Entwurf fehlertoleranter digitaler Schaltungen vorgestellt. Die als spezifische Fehlertoleranz bezeichnete Entwurfsmethode erweitert den Stand der Technik um die M{\"o}glichkeit, Fehlertoleranz gezielt f{\"u}r gew{\"u}nschte Ein- und Ausgabezuweisungen einer Schaltung bereitzustellen. Die generell sehr aufw{\"a}ndigen Maßnahmen zur Realisierung von Fehlertoleranz lassen sich so an die tats{\"a}chlich vorhandenen Zuverl{\"a}ssigkeitsanforderungen einer gegebenen Anwendung anpassen, was im Vergleich zu herk{\"o}mmlichen Verfahren zu erheblichen Kosteneinsparungen im Hinblick auf Hardware und Stromverbrauch f{\"u}hrt. Die Eingaben einer Schaltung werden dazu mit ihren zugeh{\"o}rigen Ausgaben in kritische und unkritische Signale unterteilt. F{\"u}r kritische Signale wird das gleiche Maß an Fehlertoleranz bereitgestellt, wie es auch durch das Verfahren der dreifach modularen Redundanz garantiert wird. Unkritische Signale werden nicht fehlertolerant ausgelegt, da das f{\"u}r solche Signale nicht gefordert werden muss. Im Bezug auf kombinatorische Schaltungen wird dieses Grundprinzip auf eine beliebig w{\"a}hlbare Teilmenge aller m{\"o}glichen Eingaben mit ihren zugeh{\"o}rigen Ausgaben angewendet. Die nicht zu sch{\"u}tzenden, unkritischen Signale werden zu Optimierungszwecken genutzt. Genau diese Freiheit im Entwurfsprozess erm{\"o}glicht beim Entwurf fehlertoleranter Schaltungen signifikante Kosteneinsparungen, die bislang durch andere Verfahren nicht ber{\"u}cksichtigt wurden. Bei sequentiellen Schaltungen wird das Konzept auf Eingabefolgen und ihre entsprechend zugeh{\"o}rigen Ausgabefolgen abgebildet. Ab einem bestimmten Zustand werden in Schaltungen, die nach diesem Prinzip entworfen wurden, alle als kritisch eingestuften Eingabefolgen fehlertolerant verarbeitet, woraufhin die sequentielle Schaltung entsprechend fehlertolerante Ausgabefolgen liefert. Die L{\"a}nge der kritischen Eingabefolgen und die Anzahl der Zust{\"a}nde, von denen aus eine fehlertolerante Verarbeitung der Eingaben gefordert wird, ist beliebig w{\"a}hlbar. Neben der Beschreibung des Grundkonzeptes der spezifischen Fehlertoleranz f{\"u}r kombinatorische und sequentielle Schaltungen beinhaltet die Arbeit Erweiterungen, mit denen sich die durch das Verfahren bereitgestellte Fehlertoleranz erh{\"o}hen l{\"a}sst. Es wird zudem erl{\"a}utert, wie die spezifische Fehlertoleranz ohne besonderen Aufwand mit Hilfe g{\"a}ngiger Werkzeuge im Schaltungsentwurf umgesetzt werden kann. Vom Entwerfer werden dazu keine speziellen Kenntnisse {\"u}ber das eigentliche Verfahren vorausgesetzt. Anhand experimenteller Ergebnisse wird auch gezeigt, welche Einsparungen sich durch die spezifische Fehlertoleranz im Vergleich zu herk{\"o}mmlichen Verfahren aus diesem Bereich ergeben. Dazu wurden verschiedene Benchmark-Schaltungen mit der spezifischen Fehlertoleranz implementiert und ihre Gesamtfl{\"a}chen den Fl{\"a}chen entsprechender Schaltungen, die nach dem Prinzip der dreifach modularen Redundanz entworfen wurden, gegen{\"u}bergestellt.}, subject = {Integrierte Schaltung; Zuverl{\"a}ssigkeit; Fehlertoleranz; Fehlertoleranz; Dreifach modulare Redundanz; Fl{\"a}chenreduzierung; Digitalschaltung; TMR; Fault tolerance; Triple modular redundancy; Reduction of area; Digital circuit; TMR}, language = {de} }