@phdthesis{Kreiser2015, author = {Kreiser, Dan}, title = {Optimierung und Erweiterung des IEEE 802.15.4a UWB-Standards f{\"u}r den Einsatz in Automatisierungssystemen}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-38703}, school = {BTU Cottbus - Senftenberg}, year = {2015}, abstract = {Der Einsatz funkbasierter Steuerungs- und {\"U}berwachungssysteme wird sich in den n{\"a}chsten Jahren in der Automatisierungsindustrie wesentlich erh{\"o}hen. Funkbasierte Systeme sind flexibel, das heißt skalierbar, leicht rekonfigurierbar und mobil. Außerdem sind Funksysteme kosteng{\"u}nstig, insbesondere bei der Wartung. Dennoch m{\"u}ssen diese Systeme hohen Anforderungen gen{\"u}gen, wie Sicherheit, Zuverl{\"a}ssigkeit, Energieverbrauch, Geschwindigkeit und Wirtschaftlichkeit. Besonders wichtig f{\"u}r den Einsatz drahtloser Funktechnologien in Automatisierungssystemen ist die harte Echtzeitf{\"a}higkeit bei Zykluszeiten im Bereich von unter 1 ms bei Netzwerkgr{\"o}ßen von bis zu 127 Knoten bei einer bidirektionalen Kommunikation mit einer Nutzdatenmenge von bis zu 48 Byte je Sensorknoten. Eine weitere Herausforderung ist die Integration dieser Systeme in bestehende Infrastrukturen, wo Koexistenz mit bereits vorhandenen drahtlosen Systemen ein kritischer Faktor ist. Ziel dieser Arbeit ist es, die IR-UWB Funktechnik basierend auf dem Standard IEEE 802.15.4a so zu verbessern, dass sie die hohen Anforderungen der Automatisierungsindustrie erf{\"u}llt. Dabei soll gew{\"a}hrleistet werden, dass die Abweichungen im Vergleich zum Standard m{\"o}glichst gering ausfallen und dass die Vorgaben der Regulierungsbeh{\"o}rden nicht verletzt werden. Diese Anforderungen begrenzen die M{\"o}glichkeiten der Optimierungen stark, was die Aufgabe noch schwieriger macht, aber zugleich wird damit sichergestellt, dass die L{\"o}sungen auch in realen Systemen eingesetzt werden k{\"o}nnen. In dieser Arbeit wurden sowohl komplexe theoretische Ans{\"a}tze als auch Optimierungen der Implementierung ausgearbeitet, in Matlab simuliert und in einem FPGA implementiert. Anschließend wurde ein ASIC gefertigt. Um die hohen zeitlichen Anforderungen zu erf{\"u}llen, wurden die einzelnen Teile des UWB-Frames optimiert. Um dies zu erreichen mussten neue Synchronisations- und Daten{\"u}bertragungs-Verfahren entwickelt werden. Dieses Verfahren erm{\"o}glicht eine parallele bidirektionale Kommunikation mit einer variablen Anzahl an Sensorknoten (bis zu 127). Eine Kombination verschiedener Fehlerkorrekturverfahren (Reed-Solomon-Code und Hamming-Code) wurde untersucht, um die Zuverl{\"a}ssigkeit zu erh{\"o}hen. Zus{\"a}tzlich wurde ein Fehlerkorrekturverfahren f{\"u}r tern{\"a}re Impulssequenzen mit geringem Overhead ausgearbeitet. Dieses Verfahren erlaubt eine ausreichend gute Fehlerkorrektur und erlaubt im Gegensatz zu der Fehlerkorrektur mit dem Reed-Solomon-Code das Einhalten der zeitlichen Anforderungen. Das Hauptergebnis dieser Arbeit ist ein f{\"u}r IR-UWB optimiertes {\"U}bertragungskonzept, welches eine zuverl{\"a}ssige und energieeffiziente Daten{\"u}bertragung von unter 1 ms f{\"u}r einen Master und 127 Slaves erm{\"o}glicht. Teile dieses Verfahrens wurden in Hardware gefertigt und experimentell evaluiert. Wenn alle vorgeschlagenen Optimierungen verwendet werden, kann die Zykluszeit im Vergleich zum IEEE 802.15.4a Standard, um 95\% reduziert werden. Der Energieverbrauch des gesamten Netzwerkes sinkt dabei um 65\%. Einige der vorgeschlagenen Verbesserungen wurden implementiert und f{\"u}r die {\"u}brigen wurde gezeigt, wie sie implementiert werden k{\"o}nnen. Der Einfluss weiterer Faktoren, wie die Umschaltzeit zwischen Sender und Empf{\"a}nger, und deren Auswirkungen auf den Energieverbrauch wurden untersucht. Im Rahmen dieser Doktorarbeit entstand eine standardkonforme IR-UWB Einzelchipl{\"o}sung, die um Eigenschaften erweitert wurde, die vom Standard, abweichen, aber notwendig sind um die Anforderungen der Automatisierungsindustrie zu erf{\"u}llen. Die gefertigte Variante der Einzelchipl{\"o}sung enth{\"a}lt nicht alle in dieser Arbeit vorgeschlagenen Optimierungen, ist aber dennoch in der Lage die Zykluszeit um 57\% zu verk{\"u}rzen. Obwohl dieser Chip viele zus{\"a}tzliche Features bietet, wurde die Komplexit{\"a}t und somit auch die ben{\"o}tigte Chipfl{\"a}che um 43\% reduziert.}, subject = {UWB; Synchronisierung; Automatisierungssystem; Vollduplex; Zuverl{\"a}ssig; IEEE.802.15.4a; Synchronization; Broadcast; Multicast; Ultraweitband; Synchronisierung; Automatisierungssystem; IEEE 802.15.4}, language = {de} } @phdthesis{Petrovic2013, author = {Petrovic, Vladimir}, title = {Design methodology for highly reliable digital ASIC designs applied to network-centric system middleware switch processor}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29620}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.}, subject = {Kundenspezifische Schaltung; Schaltungsentwurf; Fehlertoleranz; Entwurfsmethodik; Single Event Effects; Latchup Schutz; ASIC Entwurf; Fault-tolerance; Design methodology; Single event effects; Latchup protection; ASIC design}, language = {en} } @phdthesis{SanchezSanchez2006, author = {S{\´a}nchez S{\´a}nchez, David}, title = {Key management for wireless ad hoc networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-164}, school = {BTU Cottbus - Senftenberg}, year = {2006}, abstract = {Key management is a fundamental security service to enable secure wireless ad hoc networks (WAHN). To date existing key management solutions based on either public key infrastructures (PKI) or key pre‑distribution scheme (KPS) exhibit limitations for WAHNs. We firstly develop the Hybrid Key Management Infrastructure (HKMI) for WAHNs composed of moderate‑resource devices. The HKMI complements PKI with trust and cooperation protocols to construct an performance efficient security solution. We secondly develop the Deterministic Pairwise Key Pre-Distribution Scheme (DPKPS) for large‑scale dynamic WAHNs composed of low‑resource devices. The DPKPS applies a combinatorial design for the pre-distribution of multiple bivariate polynomial shares to WAHN nodes. Future work comprises further improving the resiliency of the DPKPS, completing a key management infrastructure on the basis of the DPKPS, the design of DPKPS‑based access control mechanisms, and the integration of the HKMI with the DPKPS in a unified key management architecture.}, subject = {Ad-hoc-Netz; Verteiltes System; Key management; Sicherheit; Schl{\"u}sselmanagement; Ad-hoc-Netz; Security; Key management; Ad hoc networks}, language = {en} } @phdthesis{Dietterle2009, author = {Dietterle, Daniel}, title = {Efficient protocol design flow for embedded systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-7848}, school = {BTU Cottbus - Senftenberg}, year = {2009}, abstract = {It is predicted that, in the next years, wireless sensor networks could be massively deployed in a wide variety of application areas, such as agriculture, logistics, automation, or infrastructure monitoring. An extremely low power consumption, high dependability, and low cost are common requirements for sensor nodes in all these applications. This can be achieved only by tiny, power-efficient microcontrollers and communication systems integrated on a single chip. Formal description techniques, such as SDL (Specification and Description Language), are suitable to formally prove properties of models designed in these languages. Code generators facilitate the automatic transformation of SDL models into software implementations, while preserving the properties of the model and, thus, achieving high system dependability. The implementations consist of the translated state machine behavior and, additionally, require a run-time environment for model execution. The objective of this work was to investigate an integrated design flow for embedded systems, which should allow the development of efficient and dependable system implementations from abstract SDL specifications. In this thesis, concepts for minimal SDL run-time environment have been devised and realized by an example implementation. Not only pure software implementations should be considered, but starting from these also the hardware/software (HW/SW) partitioning of the system should be supported. For this purpose, a cosimulation framework that allows the coupling of an instruction set simulator (ISS) with a functional SDL simulation has been investigated and prototypically implemented within the scope of this thesis. By shifting functionality to dedicated hardware components it is possible to take computational load from the microcontroller and to decrease the overall energy consumption by reducing the clock frequency and lowering the supply voltage. Due to the use of SDL, the design flow lends itself particularly to the implementation of communication protocols, and is limited to applications with soft real-time requirements. For an SDL-based design flow targeted to resource-constrained embedded systems, concepts and real implementations of minimal SDL run-time environments were lacking. Available software tools, indeed, enable the transformation of SDL models into C code, however for an efficient implementation, an integration into existing real-time operating systems (RTOS) for small microcontrollers is essential. A prototypical implementation of a run-time library for the Reflex RTOS has been created to validate our general concepts. It is about 30 \% faster and consumes less than half of the program memory compared to the operating system independent run-time environment of the tool vendor Telelogic. For simple SDL models, the application requires in total less than 8 kbytes program memory and 1 kbyte RAM. For the evaluation of design alternatives that realize different hardware/software partitionings, instruction set simulators are particularly suitable. They facilitate the identification of performance bottlenecks of the HW/SW system. Test stimuli are required in order to measure the performance and response time of systems under design. The development of an environment that generates such test signals can be a laborious task. Thus, it is reasonable, especially in the design of protocols, to use an SDL simulation of a communication network to generate these test stimuli. Such an SDL model already exists and is the basis for the implementation. The protocol implementation simulated by the ISS then becomes part of the network simulation. An efficient coupling of SDL simulations with instruction set simulators had to be investigated, and a solution is presented in this thesis. Based on the general concepts, a cosimulation framework for the ISS TSIM for the LEON2 processor was realized by the author. The joint SDL and instruction set simulation is very fast, which could be demonstrated by connecting a software implementation of the complex IEEE 802.15.3 medium access control (MAC) protocol with an SDL simulation of a network consisting of four devices. The real execution time for 10 seconds of simulation time amounted to just 50 seconds. The overall design flow was validated by means of a HW/SW implementation of the IEEE 802.15.3 wireless MAC protocol. The author designed a complete SDL model of the protocol and integrated it into Reflex. By using our cosimulation environment for the TSIM simulator, the model was partitioned into hardware and software. For the hardware part, a dedicated protocol accelerator was designed by the author. This hardware component was integrated on a single chip with the LEON2 processor and, finally, manufactured. It could be shown that the presented methodology enables the design and implementation of efficient HW/SW systems. Consequently, it can be applied to the development of dependable and energy-efficient wireless sensor nodes and other embedded systems.}, subject = {Eingebettetes System; Protocol Engineering; Cosimulation; IEEE 802.15.3; Model-based design; Protocol engineering; Cosimulation; IEEE 802.15.3}, language = {en} } @phdthesis{Krishnegowda2020, author = {Krishnegowda, Karthik}, title = {Investigation of PSSS technologies to achieve 100 Gbps and beyond}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-52055}, school = {BTU Cottbus - Senftenberg}, year = {2020}, abstract = {The requirement for wireless communication with a speed beyond 100 Gbps is growing. There are mainly two possible approaches to achieve 100 Gbps system. One approach is to target lower transmission bandwidth and very high spectral efficiency. This method requires advanced digital signal processing operations, which are power-hungry. Another possible path is to go for a high-transmission bandwidth and a moderate spectral efficiency. We decided for this direction to implement a 100 Gbps system. We have chosen parallel sequence spread spectrum (PSSS) as an analog-friendly mixed-signal modulation where most of the baseband processing is in the analog domain, and only a small part is in the digital domain. For the channel equalization, we consider an "effective channel" that takes into account the wireless channel and the effects of the transmitter and receiver hardware impairments. The influence of the nonlinear channel response was analyzed for a PSSS modulated signal by employing the RAPP model for the power amplifier. For the first time, we performed a Hardware-In-The-loop experiment using PSSS modulation in the terahertz band. A PSSS modulated signal at a chip rate of 20 Gcps with spectral efficiency of 4 bit/s/Hz is transmitted using a 230 GHz RF-frontend operating in the linear range to achieve a data rate of 80 Gbps. One more important property is that the channel estimation and equalization are performed in the analog domain. A high-speed channel equalization algorithm was developed and implemented on FPGA/ASIC, which operates at(1/10)th of PSSS symbol rate. A parallel PSSS encoder transmitter architecture was designed to work at a high chip rate, and it was implemented on FPGA /ASIC and had an energy efficiency of 0.21 pJ bit-1 on 28nm ASIC. In this Thesis, we put forward a case for the analog-friendly modulation scheme called PSSS. This scheme does not only modulates the signal but rather builds up an eco-system (such as channel estimation, equalization, and synchronization), which is responsible for the baseband operation.}, subject = {Submillimeter-wave; Broadband receiver; PHY layer; Hardware-in-the-loop; Wireless; Drahtlos; Submillimeterwelle; Breitband-Empf{\"a}nger; THz; PSSS; Drahtloses lokales Netz; Breitbandempf{\"a}nger; Hardware-in-the-loop; Terahertzbereich}, language = {en} } @phdthesis{Zeidler2013, author = {Zeidler, Steffen}, title = {Enabling functional tests of asynchronous circuits using a test processor solution}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29643}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {During the last years, the asynchronous design style has been rediscovered as a potential solution to upcoming design issues in deep-submicron technologies. However, besides the lack of commercial tools supporting this design style, one major challenge is the test of asynchronous designs. Especially their event-driven behavior leads to problems during test. Basically, the timing of asynchronous circuits is determined by gate and wire delays that are sensitive to variations of environmental parameters (process, voltage and temperature). This leads to uncertainties in the timing of the responses. Consequently, standard commercial test systems cannot be used, because such systems read the responses at specific cycles and, therefore, could reject fault-free devices. Furthermore, available hardware testers are, in principle, not designed to react to signal events from the design-under-test as it is necessary to establish asynchronous communication via handshake signalling. As a result, even simple functional tests that only apply stimuli and read the responses of the design-under-test cannot be realized without preparatory measures. This work addresses these issues and proposes a concept to enable functional tests of asynchronous designs. The concept is based on a special test processor that provides generic interfaces used to establish asynchronous handshake communication with a device-under-test. By this, elastic functional tests can be realized that overcome the static timing of conventional tests and emulate the real operating environment of the design. Apart from the generic test processor architecture, an essential part of the concept deals with the establishment of the processor as a stand alone or embedded test equipment. A workflow is provided that describes how the device-under-test can be embedded into the test processor environment for performing the tests. Besides the interconnection between the asynchronous design and the test processor, this especially includes the generation of programs that realize the functional tests of the design. A methodology is introduced that generates the desired programs for the processor from a standard functional simulation of the design-under-test. Based on the generic concept, a framework including both a test processor implementation and the realization of the program generation is delivered. In order to evaluate the entire concept, this framework has been applied to functionally test an asynchronous arithmetic-logic-unit. In combination with additional experiments, conducted to determine the required resources, it has been shown that the introduced concept is a suitable approach to test asynchronous designs.}, subject = {Asynchrones Schaltwerk; Pr{\"u}ftechnik; Fehlererkennung; Asynchrone Schaltungen; Funktionaltest; Testprozessor; Transferprotokoll; Nichtdeterminismus; Asynchronous circuits; Functional test; Test processor; Transfer protocol; Nondeterminism}, language = {en} } @phdthesis{TroyaChinchilla2004, author = {Troya Chinchilla, Alfonso Lu{\´i}s}, title = {Synchronization and channel estimation in OFDM - algorithms for efficient implementation of WLAN systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-000000566}, school = {BTU Cottbus - Senftenberg}, year = {2004}, abstract = {This Dissertation is a contribution to the design of the Synchronization and Channel Estimation algorithms in Wireless OFDM systems, paying special attention to their implementation. After investigation of the main impairments affecting OFDM in a wireless transmission, the Dissertation obtains solutions for all the blocks forming the so-called Inner Receiver. The IEEE 802.11a standard is taken in this work as a reference, since this is the first standard proposal in which OFDM is applied for wireless LAN with transmission rates of up to 54 Mbps. The low-power feature of our proposals has been demonstrated by designing an Integrated Circuit fully compatible with the IEEE 802.11a specifications. Results show that the power figures expected for our design are very competitive in comparison with the results reported by other research groups and companies working in this field.}, subject = {Drahtloses lokales Netz; OFDM; {\"U}bertragungskanal; Sch{\"a}tzung; Synchronisierung; VLSI @ IEEE 802.11; HIPERLAN/2; OFDM; {\"U}bertragungskanal; 802.11a; Kanalsch{\"a}tzung; HiperLAN2; OFDM; Synchronisation}, language = {en} } @phdthesis{Glišić2010, author = {Glišić, Srđan}, title = {Design of fully integrated 60 GHz OFDM transmitter in SiGe BiCMOS technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-22062}, school = {BTU Cottbus - Senftenberg}, year = {2010}, abstract = {The goal of this thesis is the analysis of the challenges and finding solutions for the design of mm-wave transceivers. The work presented here is focused on design of transmitter (TX) components, which are critical for the performance of the whole analog front-end. Phase-locked loop (PLL) phase noise is optimized, an image-rejection filter and a high 1 dB compression point (P1dB) power amplifier (PA) are designed. The PLL phase noise optimization is presented and different PLL topologies are compared. A new optimized recipe for calculating PLL parameters of a forth order PLL is presented. Using this approach the spurious sidebands can be reduced by up to 10 dB. The image-rejection filter chapter analyzes the challenges related to the design of the integrated image-rejection filter. The analysis presented here is the first on integrated filters for the 60 GHz band, because the previously published work dealt with on-board filters. The main problems related to the design of integrated filters arise from the low quality factor of the integrated resonators. The effects are high insertion loss and low selectivity. Two measures to reduce the insertion loss of the image-rejection filters were suggested. One is to design the filter as broadband. This measure deteriorates selectivity, so the minimum required image-rejection will limit the width of the passband. The second measure is to design the filter as broadband with non-equidistant transmission zeros (i.e. asynchronously tuned filter). This measure will improve both the insertion loss and the image-rejection. The challenges related to the design of mm-wave PAs with high P1dB are analyzed and the procedure of the PA design is presented. The difficulties related to the PA design and layout are discussed and optimum solutions presented. Limits of different power combining techniques for integrated PAs are discussed. Effects of poor on-chip ground connection are analyzed. Different causes for P1dB degradation are analyzed. The produced PA features a differential cascode topology. The layout is symmetrical and presents a virtual ground on the symmetry line for the differential signal. The optimized schematic and a symmetrically drawn layout resulted in a 17 dBm measured P1dB. It was the highest reported P1dB in 60 GHz SiGe PAs when it was published. The fully integrated TX was used for data transmission with data rate of 3.6 Gbit/s (with coding 4.8 Gbit/s) over 15 meters. This is the best result in the class of 60 GHz AFEs without beamforming.}, subject = {OFDM; Hochfrequenztechnik; Sender; 60 GHz; Leistungsverst{\"a}rker; SiGe; OFDM; Transmitter; 60 GHz; Power Amplifier; SiGe; OFDM}, language = {en} } @phdthesis{Krstic2006, author = {Krstic, Milos}, title = {Request-driven GALS technique for datapath architectures}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-000000888}, school = {BTU Cottbus - Senftenberg}, year = {2006}, abstract = {In this thesis a novel Globally Asynchronous Locally Synchronous (GALS) technique applicable to wireless communication systems and generally to datapath architectures is presented. The proposed concept is intended for point-to-point communication with very intensive but bursty data transfer. This concept is based on a request-driven operation of locally synchronous modules. The key idea is that a module can use the input request signal as its clock while receiving a burst of data. The developed GALS technique is applied to the design of an IEEE 802.11a compliant baseband processor with the aim to alleviate the problems of system integration, power consumption and electro-magnetic interference. The GALS design was compared with a synchronous version of the baseband processor. In our experimental setup we have measured a 1\% reduction in dynamic power consumption, 30\% reduction in instantaneous supply voltage variations, and 5 dB reduction in spectral noise.}, subject = {GAL ; GALS; Systemintegration; Asynchroner Entwurf; EMI; BIST}, language = {en} } @phdthesis{Wang2008, author = {Wang, Li}, title = {Millimeter-wave Integrated Circuits in SiGe:C Technology}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-5993}, school = {BTU Cottbus - Senftenberg}, year = {2008}, abstract = {During the last decades the research and implementation of integrated circuits in W-band (Frequencies from 75 GHz to 111 GHz) or frequencies beyond were mainly dominated by GaAs technologies due to their high-performance devices. However, the low-cost requirement of commercial consumer products limits the application of GaAs technologies. Recently, the advents of 200 GHz fT SiGe:C technologies pave the way for realizing the millimeter-wave circuits with their lower cost and excellent performance. This work is focused on the design and implementation of circuits in IHP's low-cost SiGe:C technology at W-band and frequencies beyond. Different types of high-speed frequency dividers as benchmarking circuits are designed and measured to show the speed and power performance of the SiGe technology in this work. Furthermore, this work includes the design and implementation of 77 GHz/79 GHz automotive radar front-end circuits. The results are compared with the state-of-the-art to demonstrate the performance of the circuit and technology. The aim is to show the design techniques and the possibility of adopting IHP's low-cost SiGe:C technology to realize high performance circuits for high-speed applications such as future automotive radar system.}, subject = {Integrierte Mikrowellenschaltung; Silicium; Germanium; MMiC; Integrierte Millimeterwellenschaltung; Millimeter-wave; IC; SiGe; HBT; W-band}, language = {en} }