@phdthesis{Krishnegowda2020, author = {Krishnegowda, Karthik}, title = {Investigation of PSSS technologies to achieve 100 Gbps and beyond}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-52055}, school = {BTU Cottbus - Senftenberg}, year = {2020}, abstract = {The requirement for wireless communication with a speed beyond 100 Gbps is growing. There are mainly two possible approaches to achieve 100 Gbps system. One approach is to target lower transmission bandwidth and very high spectral efficiency. This method requires advanced digital signal processing operations, which are power-hungry. Another possible path is to go for a high-transmission bandwidth and a moderate spectral efficiency. We decided for this direction to implement a 100 Gbps system. We have chosen parallel sequence spread spectrum (PSSS) as an analog-friendly mixed-signal modulation where most of the baseband processing is in the analog domain, and only a small part is in the digital domain. For the channel equalization, we consider an "effective channel" that takes into account the wireless channel and the effects of the transmitter and receiver hardware impairments. The influence of the nonlinear channel response was analyzed for a PSSS modulated signal by employing the RAPP model for the power amplifier. For the first time, we performed a Hardware-In-The-loop experiment using PSSS modulation in the terahertz band. A PSSS modulated signal at a chip rate of 20 Gcps with spectral efficiency of 4 bit/s/Hz is transmitted using a 230 GHz RF-frontend operating in the linear range to achieve a data rate of 80 Gbps. One more important property is that the channel estimation and equalization are performed in the analog domain. A high-speed channel equalization algorithm was developed and implemented on FPGA/ASIC, which operates at(1/10)th of PSSS symbol rate. A parallel PSSS encoder transmitter architecture was designed to work at a high chip rate, and it was implemented on FPGA /ASIC and had an energy efficiency of 0.21 pJ bit-1 on 28nm ASIC. In this Thesis, we put forward a case for the analog-friendly modulation scheme called PSSS. This scheme does not only modulates the signal but rather builds up an eco-system (such as channel estimation, equalization, and synchronization), which is responsible for the baseband operation.}, subject = {Submillimeter-wave; Broadband receiver; PHY layer; Hardware-in-the-loop; Wireless; Drahtlos; Submillimeterwelle; Breitband-Empf{\"a}nger; THz; PSSS; Drahtloses lokales Netz; Breitbandempf{\"a}nger; Hardware-in-the-loop; Terahertzbereich}, language = {en} } @phdthesis{MunozHernandez2025, author = {Mu{\~n}oz Hernandez, Hector Gerardo}, title = {Enhancing single-instruction multiple-threads FPGA-based processors with high-bandwidth-memory}, doi = {10.26127/BTUOpen-7130}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-71301}, school = {BTU Cottbus - Senftenberg}, year = {2025}, abstract = {The gap between memory bandwidth and processing power has been expanding continuously. Not long ago, some memory technology initiatives have been proposed in order to bridge this disparity. One of the most promising solutions comes in the form of 3D stacked memories like High-Bandwidth Memory (HBM). By adding several and wider memory channels that can do memory transactions in parallel, these memories increase significantly the data throughput and aim to close the aforementioned gap. A popular way to prototype and test these memories is to integrate them with Field Programmable Gate Arrays (FPGAs) due to their high reconfigurability. Graphic Processing Units (GPUs) are another inherently parallel targeted hardware, and so some advances in integrating GPUs with HBM are already present in the industry. This new technology integration brings a paradigm shift because in order to fully take advantage of the parallel nature of HBM, the hardware design has to also support this highly parallel data throughput. While GPUs provide high data processing parallelism, FPGAs are known for their flexibility. Intellectual Property (IP) blocks are an example of this flexibility, because they are a bundle of Hardware Description Language (HDL) code which can be included in an existing implementation of an FPGA, adding functionality to it. Soft-IP-cores implemented on reconfigurable hardware, are a solution that offers advantages from both worlds, where a soft-GPU could be hosted in an FPGA. There is, however, a gap in knowledge on how 3D stacked memories support soft-GPU-cores. This thesis analyses this gap and provides insights into how HBM memories can be exploited in soft-GPU-cores. To accomplish such an endeavor, this thesis presents, evaluates, and analyzes a complete open-source environment that consists of a soft-GPU with HBM compatibility. The contributions are composed of several different tools ranging from the model simulator, to easy-to-use implementation flow on real hardware. The environment also includes a roofline model which is used to analyze how applications from different domains behave and can be optimized in the custom hardware.}, subject = {Field programmable gate array; Soft-core; High-bandwidth-memory; RISC-V; Embedded systems; FPGA; HBM; Eingebettete Systeme}, language = {en} } @phdthesis{Veleski2022, author = {Veleski, Mitko}, title = {A cross-layer framework for adaptive processor-based systems regarding error resilience and power efficiency}, doi = {10.26127/BTUOpen-6145}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-61450}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1\% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15\%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.}, subject = {Processor; Cross-layer; Power; Resilience; Prozessoren; Energieeffizienz; Leistungseffizienz; Fehlerresilienz; Prozessor; Modell; Energieeffizienz; Fehlertoleranz}, language = {en} } @phdthesis{Ampadu2025, author = {Ampadu, Kwame Owusu}, title = {Road traffic gesture autonomous integrity monitoring}, doi = {10.26127/BTUOpen-7222}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-72226}, school = {BTU Cottbus - Senftenberg}, year = {2025}, abstract = {Sensor enabled smart vehicles are predicted to succeed beyond human capabilities, thereby eliminating handling errors intrinsic to human driving. Driverless vehicles must be capable of detecting and responding to exaggerated ad hoc bodily movements that humans use to maintain road traffic safety. These nonverbal communication cues may be used to ease traffic flow, control infotainment systems or restore minimal risk conditions. The integration of sensor fusion techniques and high-quality benchmark datasets coupled to high throughput general purpose graphics processing units is spawning complex heavyweight algorithms useful for traffic scene understanding. These advanced methods are expensive in terms of costs related to hardware, software and energy consumption. Yet, the autonomous vehicle lacks the ability to participate in gestural exchanges. Following extensive evaluations of recent technological advancements in gesture detection and recognition in dynamic traffic environments, a new communication technology has been created for interaction between autonomous and traditional vehicles at unsignalized four-way intersections. This system operates without relying on most conventional navigation sensors and algorithms, allowing autonomous vehicles to communicate with traditional vehicles at intersections through in-vehicle traffic lights that utilize fuzzy logic. The algorithm implemented on low-cost microcontrollers can disperse road traffic and also perform extended blind spot detection. A single sensor is utilized, which remains largely unaffected by adverse weather conditions. The system requires no internet connectivity. It also avoids the need for large scale or long-term data storage, such as the driving cloud platform, ensuring backward compatibility with traditional vehicles. Simulations were conducted based on the order and direction of arrival at three junctions. Results have shown that autonomous vehicles at four-legged intersections, can now communicate with human drivers at a much lower cost achieving precise location classification and lane dispersion in under 30 seconds. This pioneering innovation presents an opportunity to turn every four-way intersection into a signalized junction at zero cost to governments.}, subject = {Advanced Driver Assistance System (ADAS); Autonomous vehicle; Fuzzy logic; Gesture recognition; In-vehicle traffic light; Fahrerassistenzsystem; Autonomes Fahrzeug; Fuzzy-Logik; Gestenerkennung; Fahrzeugintegrierte Ampel; Autonomes Fahrzeug; Fahrerassistenzsystem; Gestenerkennung; Fuzzy-Logik}, language = {en} }