@phdthesis{Le2024, author = {Le, Quang Huy}, title = {Empirical large-signal modeling of 22-nm FDSOI CMOS transistors in RF/mm-Wave range}, doi = {10.26127/BTUOpen-6807}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-68077}, school = {BTU Cottbus - Senftenberg}, year = {2024}, abstract = {In recent years, the deployment of the 5th generation (5G) telecommunications network has fuelled growing interest in low-power and low-cost wireless transceivers in the radio frequency integrated circuits (RFIC) market. With silicon-based complementary- metal-oxide-semiconductor (CMOS) technologies, the digital circuitries and the RF front-end can be implemented monolithically as a single system-on-chip (SoC). In such scenario, advanced fully depleted silicon-on-insulator (FDSOI) technology has emerged as a potential candidate to meet the market demand. In particular, the industry's 22-nm FDSOI technology has been continuously matured in accordance with the development roadmap for 5G mm-wave applications. Research in transistor device modeling is of high importance to support the technology development process. Moreover, a large-signal model that accurately captures and reflects the transistor's nonlinear behaviour is essential for circuit design and reliability analysis. Hence, this thesis deals with measurement-based approach, i.e., empirical modeling, to develop a suitable large-signal model for the mm-wave transistors in 22-nm FDSOI technology platform. A versatile and efficient large-signal model based on the Angelov (Chalmers) model is proposed in this work. Besides, artificial neural network (ANN) is utilized to model the gate charge of the transistors. Moreover, the systematic modeling procedure addresses many important issues to ensure good model-to-hardware correlation. The proposed model is well validated for small-signal operation up to 110 GHz. Furthermore, by means of non- 50-Ω large-signal measurements, the excellent model validity to predict the nonlinear distortions of the FDSOI transistors is also comprehensively demonstrated. Finally, to evaluate the model applicability in RF circuit design, the proposed model is implemented in a commercial circuit simulator for the design of a wideband 22-nm FDSOI power amplifier.}, subject = {mm-wave; 22-nm; FDSOI; CMOS; ANN; Large-signal model; KNN; Großsignalmodell; mm-Wellen; Modellierung; Großsignalverhalten; Transistor; SOI-Technik; CMOS-Schaltung; Milimeterwelle; 5G}, language = {en} } @phdthesis{Kared2025, author = {Kared, Trusha}, title = {Mathematical analysis, design, and validation of a high dynamic range, low noise differential mixer using SiGe microwave transistors}, doi = {10.26127/BTUOpen-7121}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-71216}, school = {BTU Cottbus - Senftenberg}, year = {2025}, abstract = {The limits imposed by the wireless environment require the designer to consider noise, linearity, and power consumption. Bipolar technology has been the most appealing silicon technology due to its high-speed performance and well-engineered base parasitics. Its high transition frequency and low base resistance have resulted in remarkable noise performance. These advantages, combined with scaling flexibility, have made bipolar devices the fundamental component of silicon RF front-ends. With the growing demand for high-performance wireless applications from satellite and radar systems to 5G infrastructure, there is a strong need for advanced mixer architectures that can deliver high isolation, gain, and low noise across wide frequency ranges. The purpose of this dissertation was to describe the differential mixer and its mathematical properties in terms of gain and noise figure, and to explore further optimizations. In fact, it turned out that the mixer design was greatly improved in terms of both the noise figure and the intercept point. The active double-balanced down-conversion mixer is built on SiGe technology. The circuit exhibits significant improvement in terms of the mixer's other performance parameter metrics. This dissertation presents a novel SiGe HBT-based differential double-balanced down-conversion mixer featuring significantly enhanced conversion gain, noise performance, linearity, dynamic range, and port-to-port isolation. Compared to existing designs, this mixer delivers outstanding performance, achieving a single-sideband (SSB) noise figure of 7 dB ± 0.4 dB, a conversion gain of 12 dB ± 1 dB, and exceptional isolation metrics RF-to-IF isolation greater than 35 dB, with LO-to-RF and LO-to-IF isolation exceeding 50 dB across the 0.5 GHz to 1.8 GHz frequency range. Furthermore, it has an Input third-order intercept point (IP3) of +4.7 dBm, an output third-order intercept point (OIP3) of +15 dBm, and a 1 dB compression point of -8 dBm. This high-performance down-conversion double-balanced mixer integrates several state-of-the-art innovations. A transformer-free single-ended-to-differential conversion enhances efficiency and eliminates unnecessary components at the RF stage. The dual-feedback linearization technique optimizes impedance matching while suppressing nonlinear distortion, ensuring superior linearity. Additionally, symmetrical active device layout and advanced multilayer PCB technology significantly mitigate LO-to-RF feedthrough, reducing crosstalk and maximizing port-to-port isolation. These advancements collectively result in a highly efficient, low-noise, and exceptionally linear mixer architecture, setting a new benchmark in SiGe HBT-based mixer technology rather than relying on noisy CMOS technology. Due to its higher fabrication complexity, lower yield at advanced nodes, and the necessity for more complicated design tactics in high-frequency applications, CMOS technology in small quantities is ultimately more costly than SiGe HBT-based designs. Although CMOS excels in low-power applications and large-scale digital integration, SiGe HBT remains a reasonably affordable option for high-performance RF}, subject = {Down-conversion double balanced mixer; Noise figure; Dynamic range; Marchand balun; LO mixing core; Doppelt balancierter Abw{\"a}rtsmischer; Rauschmaß; Dynamikbereich; Marchand-Balun; LO-Mischkern; Heterobipolartransistor; Siliciumhalbleiter; Germaniumlegierung; Mischer ; Rauschmessung}, language = {en} } @phdthesis{Biereigel2022, author = {Biereigel, Stefan}, title = {Radiation-tolerant all-digital clock generators for high energy physics}, doi = {10.26127/BTUOpen-6088}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-60886}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP). Clock synthesis and the synchronization of systems on the scale of large experimental detectors is an important aspect of their successful implementation and a necessity for achieving their anticipated performance. Developments in this area to increase radiation tolerance and performance are motivated by emerging requirements for clock generation and distribution. The thesis reviews the requirements of existing and emerging systems with regards to radiation-tolerant clock generation. To characterize clock generation circuits and adequately assess their conformity with the identified requirements in radiation tests, a number of methods and instrumentation setups are developed and characterized. The presented approaches combine aspects of digital programmable logic, analog circuit design and and digital signal processing concepts. To address design challenges in deep submicron CMOS nodes, the design of radiation-tolerant all-digital PLL and CDR circuits is explored in this thesis. These circuits promise opportunities to improve the radiation tolerance of clock generators, and hence this thesis devises the design of a radiation-tolerant ADPLL/CDR circuit compatible with requirements of high energy physics (HEP) electronics. Using radiation testing, the sensitivity of the circuits is studied and mitigation strategies for identified limitations are discussed. Three such ADPLL/CDR circuits are developed and tested in the form of macro blocks targeting applications in frontend ASICs for high energy physics. The circuits demonstrate jitter performance, power efficiency and radiation tolerance comparable to or better than currently used conventional PLL circuits. As a final aspect, the improved testing instrumentation and methodology developed within this thesis is applied to uncover a previously unrecognized radiation sensitivity in a conventional, radiation-hardened clock generator circuit. An integrated planar on-chip inductor is experimentally identified as responsible for this sensitivity. Irradiation tests are performed to study and characterize the nature of this sensitivity. The results suggest that energy deposition, likely within dielectric materials surrounding the inductor wiring, alters the inductor's terminal impedance. This stimulates frequency errors with long recovery times in the oscillator. The manifestation of this effect in HEP radiation environments is studied using proton irradiation, where a mitigation strategy is experimentally validated. A reduction of the impact of this sensitivity is demonstrated. To help conclusively identifying the underlying mechanism responsible for the sensitivity within the inductor itself, further research opportunities are suggested.}, subject = {All-digital; Phase-locked loop; Clock-data recovery; High-energy physics; Integrated circuit; Phasenregelschleife; Hochenergiephysik; Datenr{\"u}ckgewinnung; Integrierte Schaltungstechnik; Zuverl{\"a}ssigkeit; Hochenergiephysik; Integrierte Schaltung; Taktr{\"u}ckgewinnung; Phasenregelkreis; Zuverl{\"a}ssigkeit}, language = {en} } @phdthesis{Rumiantsev2014, author = {Rumiantsev, Andrej}, title = {On-Wafer calibration techniques enabling accurate characterization of high-performance silicon devices at the mm-wave range and beyond}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-30659}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {This work addressed the challenges of accurate mm-wave characterization of devices fabricated in advanced semiconductor technologies. It developed the in-situ calibration solution that is easy to be implemented for silicon technologies. The new technique was verified up to 110 GHz on three difference processes: high performance SiGe:C BiCMOS from IHP Microelectronics (Germany), BiCMOS9MMW from STMicroelectronics (France), and RF CMOS 8SF from IBM Microelectronics (USA). The measurement frequency was solely limited by the capability of the test equipment. Practical results demonstrated that proposed in-situ calibration significantly outperforms the convention method independently on the process specifics and complexity. Some important aspects of the on-wafer S-parameter measurement assurance were presented as well. The discussion included the analysis of the calibration residual errors caused by the improper boundary conditions of coplanar calibration standards and the impact of the RF probe tip design. In conclusion, some suggestions for further accuracy improvement of the proposed method are given.}, subject = {BICMOS; Wafer; Schaltungsentwurf; S-Parameter; On-Wafer Charakterisierung; On-Wafer Kalibriermethoden; BiCMOS; CMOS; S-parameters; On-wafer characterization; On-wafer calibration; BiCMOS; CMOS}, language = {en} } @phdthesis{Apte2020, author = {Apte, Anisha}, title = {A new analytical design method of ultra-low-noise voltage controlled VHF crystal oscillators and it's validation}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-51386}, school = {BTU Cottbus - Senftenberg}, year = {2020}, abstract = {The design of high Q oscillators, using Crystals at lower frequencies, (and dielectric resonators at much higher frequencies), has long been considered a black art. This may be due to the fact that a systematic approach with optimized design guideline for crystal oscillators could not be found after extensive literature search. In this dissertation, after analyzing the first crystal oscillator by W.G. Cady (1921), other high performance crystal oscillators will be discussed, analyzed and calculated. A single transistor crystal oscillator design as used by HP (Hewlett Packard) in one of their designs, the HP10811A is considered in this thesis for mathematical analysis and CAD (Computer aided Design) simulation. This was also measured on state-of-the-art signal source analyzer. After validation, this design is scaled to 100MHz, the frequency of interest for this dissertation. Though most designers use a single transistor based oscillator circuit, it is not an optimized design because of limited control over key design parameters such as loop gain, dc current etc. This dissertation is an attempt to overcome the limitation due to the single transistor circuit and to give a step by step procedure, explaining the significance of a two transistor design with thorough analysis and design simulation results. This two stage transistor circuit is also not yet a best solution in terms of phase noise performance and output power, and some add-on circuitry will be needed for an optimized performance. An important contribution of this work is to show that since the voltage gain is the ratio of the collector resistor and the emitter resistor, the performance is practically independent of the VHF transistor and gives better control over various parameters of the oscillator, in order to optimize the design. A grounded-base amplifier is then introduced and added for improving the isolation and the output power. Unlike most oscillators, that take the output from the collector, a novel concept introduced by Rohde [14], is incorporated here, where the crystal is used as a filter that is then connected to the grounded base amplifier, a technique which many companies have been using. This dissertation will show that this technique increases the output power without significantly affecting the phase noise. Such a validation is needed for better understanding and as per my knowledge, has not been done so far. For the oscillator, the tuning diode sensitivity and flicker noise contribution are also taken into consideration, by calibrating the mathematics and its validation is shown. Crystal resonators of the type AT and stress-compensated (SC) cut devices will be considered as they give the best performance. The one port Colpitts type oscillator is considered first and the two port two transistor design later. Both will need a post amplifier/buffer stage. A complete step by step design procedure for an optimized 100MHz crystal oscillator is then presented. For completeness, CAD Simulation and Experimental results are provided for 10 MHz, 128 MHz and 155 MHz VCO circuits.}, subject = {Quartz crystal; Crystal oscillator; Phase noise; Reference source; Voltage controlled; Quarzkristall; Kristalloszillator; Phasenrauschen; Referenzquelle; Spannungsgesteuert; Quarzoszillator; UKW; CAD}, language = {en} } @phdthesis{Luo2018, author = {Luo, Peng}, title = {GaN HEMT modeling including trapping effects based on Chalmers model and pulsed S-parameter measurements}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-45981}, school = {BTU Cottbus - Senftenberg}, year = {2018}, abstract = {Although GaN HEMTs are regarded as one of the most promising RF power transistor technologies thanks to their high-voltage high-speed characteristics, they are still known to be prone to trapping effects, which hamper achievable output power and linearity. Hence, accurately and efficiently modeling the trapping effects is crucial in nonlinear large-signal modeling for GaN HEMTs. This work proposes a trap model based on an industry standard large-signal model, named Chalmers model. Instead of a complex nonlinear trap description, only four constant parameters of the proposed trap model need to be determined to accurately describe the significant impacts of the trapping effects, e.g., drain-source current slump, typical kink observed in pulsed I/V characteristics, and degradation of the output power. Moreover, the extraction procedure of the trap model parameters is based on pulsed S-parameter measurements, which allow to freeze traps and isolate the trapping effects from self-heating. The model validity is tested through small- and large-signal model verification procedures. Particularly, it is shown that the use of this trap model enables a dramatical improvement of the large-signal simulation results.}, subject = {GaN HEMTmodeling; Trapping effect modeling; Drain-lag effect; GaN HEMT Modellierung; Trapping-Effekt Modellierung; Drain-Lag Effekt; Galliumnitrid; HEMT; Großsignalverhalten}, language = {en} } @phdthesis{Andrei2018, author = {Andrei, Andreea Cristina}, title = {Untersuchung und Optimierung robuster und hochlinearer rauscharmer Verst{\"a}rker in GaN-Technologie}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-44782}, school = {BTU Cottbus - Senftenberg}, year = {2018}, abstract = {Die n{\"a}chste Generation von integrierten Sende- und Empfangsystemen erfordert sowohl robuste rauscharme Verst{\"a}rker als auch Leistungsverst{\"a}rker auf einem einzelnen Chip. Die GaN-HEMT-Technologie hat bisher gezeigt, dass sie durch ihre hohen Durchbruchspannungen, die hohe Elektronenbeweglichkeit und die niedrige Rauschzahl ein guter Kandidat f{\"u}r die Realisierung solcher Systeme ist. Diese Arbeit besch{\"a}ftigt sich mit hochlinearen und robusten rauscharmen Verst{\"a}rkern, welche in Sender-Empf{\"a}nger-Systeme integriert werden k{\"o}nnen. Zuerst wird der GaN HEMT charakterisiert. Die Eigenschaften von Transistoren werden w{\"a}hrend des Burn-in Prozesses und gepulster Anregung mit hoher {\"U}berlast am Eingang analysiert. Damit werden die Grundlagen f{\"u}r das Verst{\"a}ndnis des Verhaltens eines Verst{\"a}rkers w{\"a}hrend und nach der {\"U}bersteuerung am Eingang gelegt. Der Hauptteil dieser Arbeit zeigt die Entwicklung und die Charakterisierung von robusten rauscharmen Verst{\"a}rkern. Dar{\"u}ber hinaus wird ein neues Konzept f{\"u}r die Steigerung der Robustheit entwickelt, gemessen und charakterisiert. Das Konzept verwendet eine neuartige Zusammenschaltung zweier Transistoren am Verst{\"a}rkereingang, wodurch die Spannungsfestigkeit gegen{\"u}ber hohen Leistungspegeln gesteigert wird. Damit konnten H{\"o}chstwerte von +44dBm mit CW-Anregung und +47dBm mit gepulster Anregung am Verst{\"a}rkereingang ohne Besch{\"a}digung demonstriert werden.}, subject = {GaN HEMT; Rauscharme Verst{\"a}rker; Robustheit; Stacked Verst{\"a}rker; {\"U}bersteuerung mit hoher Eingangsleistung; GaN HEMT; Low noise amplifier; Ruggedness; Stacked amplifier; Input power overdrive; Rauscharmer Verst{\"a}rker; Galliumnitrid; HEMT; Robuste Regelung}, language = {de} } @phdthesis{PashminehAzar2017, author = {Pashmineh Azar, Sara Toktam}, title = {Design and analysis of integrated CMOS high-voltage drivers in low-voltage technologies}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-42515}, school = {BTU Cottbus - Senftenberg}, year = {2017}, abstract = {With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors. Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36\% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40\% and 46\%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail. In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66\%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.}, subject = {Integrated CMOS; High-Voltage; Driver; Buck-Converter; Integrierte CMOS; Hochspannung; Treiber; Abw{\"a}rtswandler; CMOS-Schaltung; Abw{\"a}rtsumsetzer; Hochspannung; Treiberschaltung}, language = {en} } @phdthesis{Griebel2021, author = {Griebel, Wolfgang}, title = {Weltraumgeeignete 5MHz Quarzoszillatoren mit maximaler Stabilit{\"a}t zwischen 1 und 10 Sekunden}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-55204}, school = {BTU Cottbus - Senftenberg}, year = {2021}, abstract = {The dissertation covers the physical, design, simulation and measurement aspects of extremely high Q precision oscillators for space applications. Existing design approaches and methods are evaluated, and it is shown that only physically complete models can deliver a good agreement between theory and experiments. A prototype was built showing very good phase noise and stability.}, subject = {Phase Noise; Crystal Oscillator; Nonlinear; Design Method; Allen Variance; Phasenrauschen; Quarzoszillator; Nichtlinear; Entwurfsmethode; Allen Varianz; Quarzoszillator; Raumfahrt; Phasenrauschen; Systementwurf}, language = {en} } @phdthesis{Poddar2014, author = {Poddar, Ajay}, title = {Slow wave resonator based tunable multi-band multi-mode injection-locked oscillators}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-31936}, school = {BTU Cottbus - Senftenberg}, year = {2014}, abstract = {In modern information technology, increasingly powerful electronic circuits are required for the targeted generation of complex signals with well-defined amplitudes and phases. In circuits of this type, oscillators frequently form the central element because of its phase noise and stability, which essentially determines the achievable precision in the signal generation. Further requirements are derived from the electronic definability of the signal properties and the operational behavior of the oscillators. Conventional oscillator circuit models autonomous circuits, mainly consist of a passive frequency-selective or phase-selective network and an active amplifier element, which together produce an oscillatory circuit via a suitable feedback. At first glance, the circuit topology seems to be quite simple, and can often be explained quite visibly. However, when it comes to describing in particular the very important phase noise dynamics and stability of oscillators, it very soon becomes apparent that highly complex structures are involved. A fundamental difficulty in the theoretical description arises due to the non-linear behavior of oscillators, the understanding of which is crucial for a reliable description of jitter and oscillator phase noise. The resonant condition of oscillators arises due to the fact that the noise in the oscillator circuit is always present in the system, which is amplified in a frequency-selective manner to the extent that a stable oscillation arises at most at a fixed frequency because of non-linear limitation of the amplification. The frequency selectivity arises due to the frequency selectivity or phase selectivity of the passive feedback path. The non-linear limitation of the amplification in the oscillator normally results in a very reliable control of the amplitude noise of the output oscillation. It is well understood that any particular oscillator's phase noise could be improved by increasing the generated signal amplitude or increasing the quality factor of the resonant network. Increasing the signal level is limited by the utilized supply voltage or the break down limits of transistors and cannot be increased further to improve the phase noise. Accordingly, the remaining phase noise, which can normally be minimized via resonating circuits with pronounced phase selectivity and therefore a high quality factor resonator, is of great importance for oscillators. Traditional high Q-factor resonators (ceramic resonator, surface acoustic wave, bulk acoustic wave, dielectric resonator, YIG resonator, Whispering gallery mode resonator, Optoelectronic resonator, etc.) are usually 3-dimensional structures and bulky for both handheld and test-measurement equipments and does not offer integration using current foundry technology. The current and later generation wireless communication market is pushing the need for miniaturization to its limits. Printed coupled transmission line resonator is a promising alternative due to its ease of integration and compatibility with planar fabrication processes but limited by its large physical size and low quality factor, making it a challenging choice to design low phase-noise oscillators. This problem is more prominent in integrated circuits (ICs) where high degrees of thin conductor losses reduce the quality factor by orders of magnitude compared to hybrid circuit technologies. This thesis describes the design and investigation of a variation of printed resonators using M{\"o}bius slow-wave and Metamaterial structures for the applications in oscillator circuits. A novel M{\"o}bius slow-wave mode-coupled structure offers additional degrees of freedom (higher Q-factor and multi-band characteristics for a given physical size) as compared to conventional transmission line printed resonators. A design study has been carried out to optimize the phase noise performance by using the novel resonant structures (mode-coupled, slow-wave, M{\"o}bius strips, evanescent mode, negative index material-Metamaterial) in conjunction with mode locking and injection locking for improving the overall performances, beyond the limits imposed by conventional limitations. The thesis also covers a broad spectrum of research on DRO and OEO ranging from practical aspects of circuit implementation and measurement, including the modeling of optical fiber delay line used as a thermally stable high Q-factor resonator structure. This thesis is research work carried out from 2004-2014, organized in 11 chapters, theoretical and experimental results documented by a range of specific measurement results and substantiated by over 200 scientific publications over dozen patents. The Metamaterial M{\"o}bius technology discussed in this thesis can open new era in the field of imaging, sensors, cloaking, energy harvesting and energy efficient microwave circuit and system Solutions.}, subject = {Oszillator; Resonator; M{\"o}bius; Phasenrauschen; Oscillator; Phase noise; M{\"o}bius; Resonator; Oszillatorschaltung; Resonator}, language = {en} } @phdthesis{Beleniotis2025, author = {Beleniotis, Petros}, title = {Physics-based trap modeling of GaN HEMTs}, doi = {10.26127/BTUOpen-6933}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-69331}, school = {BTU Cottbus - Senftenberg}, year = {2025}, abstract = {Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as the preferred choice for telecommunication system designs, owing to their superior power levels compared to their silicon counterparts, especially at high frequencies and in harsh environments. Despite these advantages, reliable GaN HEMTs have been impeded by challenges such as electron trapping, which significantly impairs transistor functionality. Accurately modeling these effects is essential for the successful deployment of GaN-based designs. Over the past 15 years, the focus has been on empirical models suitable for circuit design. These models often result in a disconnect between modeling and technological advancements, thereby limiting further optimization of device performance. This study presents a novel trap model for GaN HEMTs that combines accuracy with physical principles. The model is broadly applicable, enabling the simulation of current collapse and knee walkout under various bias conditions, and is adaptable to RF applications with exceptional accuracy, through different trap-circuit configurations. The first model configuration is effective in simulating small- and large-signal continuous-wave (CW) RF measurements. It accurately mimics the slow response of electrons in traps to voltage reductions, ensuring efficient performance in simulations where traps maintain a steady state. Its accuracy has been validated through multiple measurements, including pulsed IV, S-parameter measurements, RF power sweeps, and load pull contours. Its development was enhanced by integrating experimental data and theoretical insights, which improved its accuracy and facilitated the development of additional analytical tools, such as statistical and compact modeling for trap localization. The second configuration is advantageous for pulsed RF and switching applications, as well as high-temperature environments. This configuration enables precise characterization of the swift capture time constant, a capability previously unattainable with conventional measurement techniques. Its development followed a systematic approach, beginning with the characterization of trap levels within the band gap of the devices, followed by the application of TCAD simulations to locate the position of traps and assess their impact on device performance. Ultimately, the second trap model configuration incorporates Shockley-Read-Hall (SRH) statistics to model temperature- and bias-dependent trapping, aiming to simulate the slow gate-induced trapping observed in rugged GaN-based low-noise amplifiers (LNAs). The inclusion of SRH statistics addresses significant challenges in GaN HEMT trap modeling.}, subject = {Shockley-Read-Hall; GaN HEMT; Microwaves; Compact models; Trapping effects; Mikrowellen; Kompaktmodelle; Trapping-Effekte; HEMT; Galliumnitrid; Mikrowelle; Modellierung; Elektron}, language = {en} }