@phdthesis{Buechner2020, author = {B{\"u}chner, Steffen}, title = {Applying the stream-processing paradigm to ultra high-speed communication systems}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-52462}, school = {BTU Cottbus - Senftenberg}, year = {2020}, abstract = {In the last 30 years, communication became one of the most important pillars of our civilization. Every day terabytes of information are moved wired and wireless between computers. In order to transport this amount of data, researchers and industry increase the data rates of the underlying communication networks with impressive speed. However, such ultra-high data rates are unavailable at the communication endpoints. One reason why ultra-high data rates are still not available for the communication endpoints is their inability to handle the protocol processing at this data rate. In order to enable communication endpoints to process high-volume data streams, the protocol processing has to be parallelized and optimized on all processing levels. However, parallelization and optimization are cumbersome tasks, which are further complicated as the protocol processing is traditionally carried out by the operating system. This thesis aims at circumventing these problems by moving the protocol processing into external processing hardware and interpreting communication protocols as stream processing problems. In order to achieve ultra-high data rates at the communication endpoints, a protocol stream processing design approach was developed and evaluated. The design process is separated into implementation, soft real-time analysis, parallelization, and mapping steps, which allow a scalable protocol implementation without paradigm changes. Furthermore, a data link protocol for 100 Gbit/s wireless was developed and implemented with the new stream processing design concept, in order to show its feasibility. The data link protocol is configurable for different communication conditions and easy to parallelize by providing different granularities of packets. The proposed design-process has shown to be suitable for uncovering bottlenecks and helping with debugging the individual stages of the protocol.}, subject = {Stream processing; Ultra high speed communication systems; Communication protocols; Wireless communication; End2End100; Stromverarbeitung; Ultra-Hoch-Geschwindigkeits-Kommunikationssysteme; Kommunikationsprotokolle; Drahtlose Kommunikation; Kommunikationsprotokoll; Protokollverarbeitung ; Hochgeschwindigkeitskommunikation; End2End100}, language = {en} } @phdthesis{Walther2008, author = {Walther, Karsten}, title = {Ein ereignisbasiertes Betriebssystemkonzept f{\"u}r tief eingebettete Steuersysteme}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-7728}, school = {BTU Cottbus - Senftenberg}, year = {2008}, abstract = {In dieser Arbeit wird ein umfassendes Betriebssystemkonzept f{\"u}r tief eingebettete Steuersysteme vorgestellt. Das Konzept sieht dabei eine vollst{\"a}ndig ereignisbasierte Abarbeitung von Aufgaben vor. Nach einer breiten Dom{\"a}nenanalyse wird gezeigt, welche Vorteile der verfolgte Ansatz hinsichtlich der {\"u}blichen Randbedingungen der Zielsysteme hat. Außerdem werden praktische Ergebnisse, welche anhand einer exemplarischen Umsetzung des Konzeptes gewonnen wurde, vorgestellt.}, subject = {Eingebettetes System; Betriebssystem; Betriebssysteme; Ereignisbasiert; Eingebettete Systeme; Reflex; Operating systems; Event based; Embedded system; Reflex}, language = {de} } @phdthesis{Sieber2016, author = {Sieber, Andr{\´e}}, title = {Energiemanagement f{\"u}r drahtlose tief eingebettete Systeme : Feingranulares, faires Management zum Erreichen von Lebenszeitzielen bei knappen Energieressourcen}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-39288}, school = {BTU Cottbus - Senftenberg}, year = {2016}, abstract = {Drahtlose eingebettete Systeme haben vielf{\"a}ltige Anwendungsm{\"o}glichkeiten, sei es im Internet der Dinge oder in Sensornetzen. Diese Systeme sollen dabei ohne Eingriff von außen eine hohe Laufzeit erreichen. Die Energieversorgung und der Verbrauch spielen dabei entscheidende Rollen, sind jedoch Varianzen unterworfen. Sollen Wartungsintervalle oder Lebenszeitziele erreicht werden, ist deshalb ein dynamisches Energiemanagement unabdingbar. In dieser Doktorarbeit wird ein solcher Ansatz vorgestellt, umgesetzt und evaluiert. Im Gegensatz zu existierenden Ans{\"a}tzen werden Varianzen auf allen drei Ebenen des Managements (Energieversorgung, Energieverbrauch und Energieverwaltung) adressiert. F{\"u}r die Energieversorgung wird eine Batterie{\"u}berwachung vorgestellt, welche eine Steuerung des Verbrauchs ohne komplexe Berechnung des Ladezustands erm{\"o}glicht. Der Verbrauch des Systems wird durch einen Software-basierten Ansatz feingranular ermittelt und bezieht Varianzen durch {\"A}nderungen der Spannung und der Effizienz von Spannungswandlern ein. Die Verwaltung und Zuordnung der Energie zu Anwendungszielen erfolgt mittels dynamischer Energiebudgets und bietet verschiedene Strategien, um auf {\"A}nderungen des Bedarfs ad{\"a}quat reagieren zu k{\"o}nnen.}, subject = {Eingebettete Systeme; Drahtlose Sensornetze; Energiemanagement; Energiebewusstsein; Lebenszeitziele; Embedded systems; Wireless Sensor Networks; Energy management; Energy awareness; Lifetime goals; Eingebettetes System; Energiemanagement}, language = {de} } @phdthesis{Traue2018, author = {Traue, Jana}, title = {Fine-grained transactions for NVRAM}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-46367}, school = {BTU Cottbus - Senftenberg}, year = {2018}, abstract = {For decades, there has been a distinction between fast, volatile and slow, non-volatile memory technologies in the storage hierarchy of computer systems. While volatile memories offer a byte addressable interface, persistence was limited to slower, block-oriented media. As a consequence, processing and storing information implies copying data from the persistent storage to volatile memory and vice versa. In recent years, a new memory technology which is both byte-addressable and non-volatile has been announced: Non-Volatile Random Access Memory (NVRAM). Its unique combination of features allows processing of information exactly at the location where it is stored permanently, thereby eliminating the need for copies. Without the need to create and manage copies, data can be processed significantly faster. The processing of persistent information can be disrupted by failures, like crashes. When changes are only partially performed, data might be left in an inconsistent state. Such a situation can be avoided by creating a copy before starting to change data. That backup is restored when a failure has been detected. Such a procedure relies on a highly specific order of its operations, because the backup can only be disposed after all changes have been carried out successfully. Since NVRAM removes the need for accessing block-oriented media, it removes a major bottleneck in the processing of persistent information, especially when only small amounts of data are modified. As a result, controlling the order of operations dominates the processing performance. This thesis analyses transactional mechanisms for data on NVRAM which can guarantee that sequences of operations are either carried out as one unit or not at all. The idea is based on creating backups, as sketched above. Existing approaches for the traditional storage hierarchy use separate memory locations for backup and modified data. In a first step, the costs of applying existing procedures to NVRAM are identified. Afterwards, a novel approach which couples the versions tighter in space is presented. Enabled by the unique properties of NVRAM, this new approach is able to reduce the costs of ordering. The processing of persistent data can thereby be sped up significantly.}, subject = {NVRAM; Transactions; Cache lines; Non-volatile; Main memory; Nicht-fl{\"u}chtig; Hauptspeicher; Cache-Line; Transaktionen; NVRAM; Hauptspeicher; RAM; Transaktion; Sicherungskopie}, language = {en} } @phdthesis{Gypser2022, author = {Gypser, Philipp}, title = {Mechanisms for energy-efficient processor allocation and redistribution on manycore systems}, doi = {10.26127/BTUOpen-6385}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-63853}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {Multi- and manycore processors promise to combine high overall peak performance with moderate power consumption to meet the constantly growing demand for computational power under the energy constraints of today's CMOS technology. Future systems with manycore processors are expected to contain a huge amount of cores, which exceeds the number of processes that will run simultaneously. Consequently, processor time sharing approaches, that introduce significant overhead from regular context switches in common OS, will no longer be necessary. This work investigates mechanisms for scalable and energy-efficient spatial partitioning of multi- and manycore processor systems. In addition, it explores the implications of exclusive processor core allocation to user processes due to the absence of temporal multiplexing and offers approaches to ease the adaptation to the new programming model. The proposed mechanisms achieved fast thread allocation which motivates applications for dynamic thread allocation and benefits performance as well as energy efficiency. The efficiency control and resource revocation mechanisms detect and prevent wasteful and inefficient resource occupation from poorly optimized or malicious processes. In this way, the global efficiency of the system is optimized. The dynamic processing resource allocation and revocation handling has been integrated into a task parallel runtime system, to disburden the application programmer from manual implementation and to increase productivity.}, subject = {Manycore; Operating systems; Online profiling; Energy efficiency; Dynamic partitioning; Vielkernprozessor; Betriebssysteme; Profiling; Energie-Effizienz; Dynamische Partitionierung; Mehrkernprozessor; Betriebssystem; Partionierung; Energieeffizienz}, language = {en} } @phdthesis{SegabinazziFerreira2022, author = {Segabinazzi Ferreira, Raphael}, title = {Run-time redundancy management of processor functional units for mixed-critical scenarios}, doi = {10.26127/BTUOpen-5888}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-58886}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {Since electronics started to scale down, a growing concern about the reliability of these electronic devices has emerged. At the same time, the increased demand for high performance within the safety- and mixed-critical domains, such as the aerospace and automotive industry, motivated a shift from previous consolidated and mature technology to the new cutting edge devices with smaller feature sizes. Therefore, there is a need to improve the fault tolerance of these high-end devices so that minimum failure rates can be obeyed. Although redundancy has been a great solution for these problems, their drawbacks such as power and area overheads must be watched carefully, so that per-unit price does not extrapolate affordable limits, and the redundancy does not add more sources of error than it improves the fault tolerance. This thesis proposes an approach for run-time management of redundancy among the processor internal Functional Units (FUs) within mixed-critical scenarios, tackling the compensation of the trade-offs between fault-tolerance, power consumption, hardware usage (ageing), and hardware area (cost). With these objectives in mind, this thesis presents a concept for a dynamic processor architecture capable to enable and disable redundancy of FUs on-demand, and a software mechanism for criticality-aware management of these units for mixed-critical processes within an Operating System (OS). For this purpose, a processor design was extended with a few additional instructions that enabled different replication schemes in the processor at run-time. Furthermore, a compatible Real-Time Operating System (RTOS) is also extended to enable the desired criticality-aware management of units. Evaluating the implemented test platform when the extended processor was running bare-metal code, the latency to shift between different replication schemes was of only one instructions cycle. Furthermore, when the processor was running the adapted RTOS, the run-time overhead over the latency to switch between processes remained below 2.5\%. Meanwhile, resulting from the processor extensions, the hardware overhead remained smaller than standard full core replication schemes such as core lock-step approaches. Regarding fault tolerance, the expected failure rate of the FUs module decreased by approximately 80\% when its FUs were configured with Triple Modular Redundancy (TMR). Furthermore, when considering the whole area of the processor core, its respective failure rate decreased by about 15\% when configured these units with the same triplication scheme. Finally, it is also presented that the run-time management of FUs was likewise able to decrease the power consumption and hardware ageing for the proposed mixed-critical scenario. After all, we can say that the concept can increase fault tolerance on-demand of a processor design with moderately low hardware overhead, while it also minimises the power consumption and hardware usage (ageing) for its intended mixed-critical scenario.}, subject = {Mixed-critical scenario; Redundancy; Fault-tolerance; Run-time; Fehlertoleranz; Redundanz; Funktionseinheit; Mikroprozessor; Laufzeit; Gemischtkritische Szenarien; Laufzeit; Redundanz}, language = {en} } @phdthesis{Ilić2023, author = {Ilić, Aleksandar}, title = {Strategies for increasing maximum throughput and reducing latency in tree-based WSNs}, doi = {10.26127/BTUOpen-6498}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-64986}, school = {BTU Cottbus - Senftenberg}, year = {2023}, abstract = {This thesis deals with strategies for achieving high data throughput in wireless sensor networks that use a time division multiple access (TDMA) scheme to resolve medium access. The thesis uses a multi-sided approach that deals not only with the scheduling algorithm but also with the network layer and the interference model. The thesis proposes four solutions that significantly improve data throughput, fairness, and latency in the considered scenario. The thesis starts with an overview of state-of-the-art medium access control (MAC) protocols, emphasizing TDMA. Based on this overview, it is concluded that not much space for improvement is left in the field of schedule calculation algorithms; many such algorithms are proposed up to date, and they can achieve schedule lengths close to the theoretical minimum. However, the research also reveals a lack of in-detail evaluation and comparison of these algorithms; this makes choosing the most suitable algorithm for a particular application hard and performance estimation inaccurate. Therefore, an extensive evaluation of state-of-the-art TDMA protocols using simulations and over 200 randomly generated networks was performed to tackle this issue. The results allow choosing an appropriate algorithm and estimating performance for each specific application. Next, the problem of multiple packet transmissions during a single time slot is analyzed. State-of-the-art TDMA protocols assume that one packet can be transmitted in each slot and optimize the number of slots each node gets under this assumption. However, when nodes can transmit more than one packet, the performance of such a schedule is impaired. To solve this, the M-TreeMAC protocol is proposed; this protocol considers the actual number of packets transmitted in a time slot and optimizes the schedule accordingly. Furthermore, it is observed that the routing topology heavily impacts the schedule length created using this algorithm; an algorithm that optimizes the topology to result in the shortest schedule when M-TreeMAC is used is proposed, increasing benefits even further. Finally, the accuracy of the 2-hop interference model, commonly used by state-of-the-art TDMA scheduling algorithms, is studied and simulated using a realistic radio model based on measurement results. The results show high packet loss ratios for packets traveling a large number of hops to reach the sink. The adaptive interference model is proposed to improve the 2-hop interference model. The proposed model can increase throughput significantly in networks with a height of ten or more hops.}, subject = {WSN; TDMA; Interference; Throughput optimization; Drahtlose Sensornetzwerke; Interferenz; Maximierung des Datendurchsatzes; Zeitmultiplexverfahren; Drahtloses Sensorsystem; Funk{\"u}bertragung; TDMA; Energieeffizienz}, language = {en} } @phdthesis{Karnapke2012, author = {Karnapke, Reinhardt}, title = {Unidirectional Links in Wireless Sensor Networks}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-27210}, school = {BTU Cottbus - Senftenberg}, year = {2012}, abstract = {Experiments with wireless sensor networks have shown that unidirectional communication links are quite common. What is even more, they have also shown that the range of a unidirectional link can exceed that of a bidirectional one by far. Still, most of todays routing protocols do not use them, they only eliminate their implications. Those protocols that do use unidirectional links introduce a lot of protocol overhead. One possible conclusion that is often drawn from this fact is that it does not pay to use unidirectional links in a routing protocol. An alternative one is that the overhead produced by the protocols needs to be reduced. This thesis follows the second line of reasoning, and introduces, describes and evaluates five new routing protocols for wireless sensor networks with unidirectional links.}, subject = {Drahtloses Sensorsystem; Sensornetze; Routing; Unidirektionale Verbindungen; Wireless Sensor Networks; Routing; Unidirectional links}, language = {en} }