@phdthesis{Rizzi2024, author = {Rizzi, Tommaso}, title = {Investigation of the different abstraction levels for the design of RRAM-based systems}, doi = {10.26127/BTUOpen-6867}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-68677}, school = {BTU Cottbus - Senftenberg}, year = {2024}, abstract = {The great capabilities of modern electronics have brought in any aspect of our life innovations that were inconceivable before. This progress is enabled by a microelectronic market in continuous evolution, where novel solutions are introduced in order to fulfil the increasing requirements in terms of computing speed, energy efficiency, and area miniaturization. Among the various possibilities under the spotlight for thrusting the performance advancement in the next generation of computing systems, major chip manufacturers are carefully investigating emerging Non-Volatile Memory (eNVM) technologies, in particular Resistive Random Access Memory (RRAM). While it was originally studied as an alternative non-volatile memory medium, the research community has soon realized how this family of devices with their tunable resistance can lead to new efficient designs in a variety of applications. The protagonist of the renewed enthusiasm for this technology is the thriving Artificial Intelligence (AI) field, where RRAM can support the fabrication of analogue accelerators. More precisely, the dual nature of an RRAM array as memory block and computing unit has the potential to implement novel hardware solutions that take inspiration from the human brain to efficiently execute Artificial Neural Networks (ANNs). However, the establishment of RRAM devices in the customer market is delayed by the on-going research to optimize the fabrication process. The contrast between the unsettled underlying hardware and the great interest toward emerging RRAM-based designs resulted in a performance gap between the envisioned RRAM systems and the prototyped ones. In order to transition the RRAM technology from the academic research to real-world scenarios, more circuits need to be designed, implemented, and tested. At the same time, the complexity and cost of modern electronics production impose high reliability and performance standard on the fabricated chip that can only be met by a tight link between the circuit-level validation and any stage of the design development. Unfortunately, the available tools to support the designer at the application- and system-level do not generally offer this cross-layer interface. This work investigates how important the electrical validation can be to guide the designer by comparing the circuital reliability aspects of a traditional routing component and an alternative RRAM-based implementation. Moreover, two different approaches are proposed to bridge the gap between the electric domain and the higher abstraction layers. First, SystemC-AMS is analysed as a viable option to include analogue simulations in Electronic System Level (ESL) evaluation. Several optimization techniques are also proposed to improve the framework performance. Finally, a Pytorch/Spectre tool-chain is implemented to enable circuit-level co-simulation during the testing of ANN models. The tool-chain is validated by considering the end-to-end accuracy for two classification tasks, namely MNIST and CIFAR10 datasets.}, subject = {RRAM; Multiplexer; SystemC; In-Memory Computing; Artificial Neural Network; Resistiver Direktzugriffsspeicher; Rechnen im Speicher; K{\"u}nstliches Neuronales Netzwerk (KNN); Resistive RAM; Routing; Neuronales Netz; Entwicklung; Simulation}, language = {en} }