@phdthesis{PerezBoschQuesada2024, author = {Perez-Bosch Quesada, Emilio}, title = {In-depth electrical characterization of HfO₂-based memristive devices for their integration in CMOS-compatible neuromorphic systems}, doi = {10.26127/BTUOpen-6781}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-67815}, school = {BTU Cottbus - Senftenberg}, year = {2024}, abstract = {The rapid development of information and communication technologies is reaching critical limits that might compromise the global digitalization progress, one of the main economy pillars nowadays. Among others, limits like the end of Moore's law, derived from miniaturization issues in nano-scale devices; the need for massive data processing parallelization due to the ever-increasing amount of data generated in every single aspect of our daily routine; and the acute increase of the annual electricity consumption in data center due to energy inefficiency in their computational architectures. Therefore, the need for partial or complete migration of current computing paradigms towards more sustainable ones is of paramount importance to bypass these limits. Neuromorphic computing systems inspired by the neural and synaptic activity of the human brain irrupted as an innovative alternative to merge memory and computing units, traditionally separated following the von Neumann architecture. Emerging non-volatile memory technologies, specifically the Resistive Random Access Memory (RRAM) technology, are playing important roles in the development of new computing paradigms due to their outstanding properties, namely, fast switching, high scalability, long state retention and their multilevel-cell capabilities, among others. The later stands out as a key feature to increase memory densities at lower area cost and it lately gathered special interest concerning neuromorphic applications. Due to the uncertainty surrounding the stochastic processes governing the resistive switching of the RRAM technology, here is still scarce number of real RRAM-based hardware implementations. In this work, motivated by the impact of the inherent stochasticity of the RRAM technology on neuromorphic systems' performance, a thorough wafer-scale electrical characterization is carried out over HfO2-based RRAM devices to study their quasistatic response. Their non-idealities are identified, in a way that they could be modelled and potentially mitigated to enhance the memristive devices stability and thus, their performance carrying out multiply-accumulate (MAC) tasks, fundamental operations for the implementation of artificial intelligence (AI) applications. This characterization supports the adaptation of three physics-based compact models and an empirical study of vector-matrix multiplication (VMM) operations performed using real RRAM devices for neuromorphic applications. The impact of the devices' non-idealities on the final operation results is assessed along consecutive VMMs. This work sets the baseline of the quasistatic characterization of IHP's RRAM devices and opens the way towards real ardware neuromorphic systems with such technology.}, subject = {Vector-matrix multiplications,; Neuromorphic computing; RRAM; Non-volatile; Vektor-Matrix-Multiplikationen; RRAM; Neuromorphes Rechnen; Neuromorphing; Neuronales Netz; Resistive RAM}, language = {en} } @phdthesis{Rizzi2024, author = {Rizzi, Tommaso}, title = {Investigation of the different abstraction levels for the design of RRAM-based systems}, doi = {10.26127/BTUOpen-6867}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-68677}, school = {BTU Cottbus - Senftenberg}, year = {2024}, abstract = {The great capabilities of modern electronics have brought in any aspect of our life innovations that were inconceivable before. This progress is enabled by a microelectronic market in continuous evolution, where novel solutions are introduced in order to fulfil the increasing requirements in terms of computing speed, energy efficiency, and area miniaturization. Among the various possibilities under the spotlight for thrusting the performance advancement in the next generation of computing systems, major chip manufacturers are carefully investigating emerging Non-Volatile Memory (eNVM) technologies, in particular Resistive Random Access Memory (RRAM). While it was originally studied as an alternative non-volatile memory medium, the research community has soon realized how this family of devices with their tunable resistance can lead to new efficient designs in a variety of applications. The protagonist of the renewed enthusiasm for this technology is the thriving Artificial Intelligence (AI) field, where RRAM can support the fabrication of analogue accelerators. More precisely, the dual nature of an RRAM array as memory block and computing unit has the potential to implement novel hardware solutions that take inspiration from the human brain to efficiently execute Artificial Neural Networks (ANNs). However, the establishment of RRAM devices in the customer market is delayed by the on-going research to optimize the fabrication process. The contrast between the unsettled underlying hardware and the great interest toward emerging RRAM-based designs resulted in a performance gap between the envisioned RRAM systems and the prototyped ones. In order to transition the RRAM technology from the academic research to real-world scenarios, more circuits need to be designed, implemented, and tested. At the same time, the complexity and cost of modern electronics production impose high reliability and performance standard on the fabricated chip that can only be met by a tight link between the circuit-level validation and any stage of the design development. Unfortunately, the available tools to support the designer at the application- and system-level do not generally offer this cross-layer interface. This work investigates how important the electrical validation can be to guide the designer by comparing the circuital reliability aspects of a traditional routing component and an alternative RRAM-based implementation. Moreover, two different approaches are proposed to bridge the gap between the electric domain and the higher abstraction layers. First, SystemC-AMS is analysed as a viable option to include analogue simulations in Electronic System Level (ESL) evaluation. Several optimization techniques are also proposed to improve the framework performance. Finally, a Pytorch/Spectre tool-chain is implemented to enable circuit-level co-simulation during the testing of ANN models. The tool-chain is validated by considering the end-to-end accuracy for two classification tasks, namely MNIST and CIFAR10 datasets.}, subject = {RRAM; Multiplexer; SystemC; In-Memory Computing; Artificial Neural Network; Resistiver Direktzugriffsspeicher; Rechnen im Speicher; K{\"u}nstliches Neuronales Netzwerk (KNN); Resistive RAM; Routing; Neuronales Netz; Entwicklung; Simulation}, language = {en} } @phdthesis{KalishettyhalliMahadevaiah2023, author = {Kalishettyhalli Mahadevaiah, Mamathamba}, title = {Process development and electrical characterization of CMOS-integrated memristive devices for emerging non-volatile memory applications}, doi = {10.26127/BTUOpen-6557}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-65571}, school = {BTU Cottbus - Senftenberg}, year = {2023}, abstract = {Energy efficiency is vital for future low-power electronic applications. This ultra-low power consumption requirement enables the research beyond the conventional charge-based memories. Further, reliability, high scalability, fast switching, CMOS compatibility, high endurance, etc., are some of the characteristics envisaged by the new generation of emerging non-volatile memories (NVMs). A memristor or OxRAM is one among the many emerging NVMs, which can exhibit the aforementioned characteristics, and it has the potential to replace the power-hungry conventional NVMs. The memristive devices have the advantage of monolithic integration with the CMOS logic, which enables the widening of their application areas. Despite their various advantages, the reliability, forming voltages, and variability of the devices pose a hurdle to their wide commercial usage. Hence, it is crucial to identify these factors and mitigate them. This thesis addresses these issues through fabrication process improvements, electrical characterization techniques, and device-engineering methods. The improvements in the fabrication processes reduced the pristine state currents of the memristive devices. It impacted the reliability and resistive switching performance of the memristive devices directly. To further improve the performance, the memristive devices are integrated into the 130 nm BiCMOS baseline technology of IHP. Additionally, dedicated test structures are developed to monitor and control the fabrication process steps through in-line electrical characterization. Further, the forming current and voltage values, along with their dispersions in the 4 kbit memristive arrays, were reduced by utilizing the electrical characterization techniques. Accordingly, the forming operations were performed at high operating temperatures using incremental step pulse and verify algorithm (ISPVA). In contrast to the well-known method of increasing the current compliance (1R) or the gate voltage of the transistor (1T-1R) to increase the conduction filament size, a thin layer of Al2O3 is added. This device engineering technique reduced the variability in both LRS and HRS currents of the memristive devices. Additionally, the conduction filament properties in both states are modeled by using the quantum point contact (QPC) model. Finally, harnessing the intrinsic variability of the memristive devices for neuromorphic computing applications is demonstrated. The reliability of the devices is assessed through endurance and retention characteristics.}, subject = {Memristive devices; RRAM; ISPVA; Forming; Variability; Formierspannung; Variabilit{\"a}t; Dispersion; Leitungsdraht; Neuromorphe Anwendungen; CMOS; Nichtfl{\"u}chtiger Speicher; Memristor; Modellierung; Dispersion}, language = {en} }